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1. 发明申请

WO2008004141A2 CIRCUIT FOR DETECTING THE DUTY CYCLE OF CLOCK SIGNALS 审中-公开
标题翻译：用于检测时钟信号占空比的电路
公开(公告)号：WO2008004141A2
公开(公告)日：2008-01-10
申请号：PCT/IB2007/052033
申请日：2007-05-30
申请人： NXP B.V. , KOHSIEK, Cord-Heinrich
发明人： KOHSIEK, Cord-Heinrich
IPC分类号： H03K5/19 , G01R31/28 , G06F1/10 , H03K5/1252
CPC分类号： H03K5/19 , H03K5/1252
摘要： A circuit (100) for detecting the duty cycle of clock signals comprises an oscillator (2) whose signal can be changed into a square-wave voltage in a gate (3). In order to obtain a simple construction of the circuit (100) with improved quality of the output signals a low-pass filter (3) is provided whose output signal is situated between "low" and "high".
摘要翻译：用于检测时钟信号的占空比的电路（100）包括其信号可以在门（3）中改变成方波电压的振荡器（2）。为了获得具有改善的输出信号质量的电路（100）的简单结构，提供了一个低通滤波器（3），其输出信号位于“低”和“高”之间。

2. 发明申请

WO2011080536A1 ADJUSTABLE MOS RESISTOR 审中-公开
标题翻译：可调电阻
公开(公告)号：WO2011080536A1
公开(公告)日：2011-07-07
申请号：PCT/IB2009/055956
申请日：2009-12-28
申请人： NXP B.V. , KOHSIEK, Cord-Heinrich
发明人： KOHSIEK, Cord-Heinrich
IPC分类号： H03H11/24
CPC分类号： H03H11/245
摘要： A variety of circuits, methods and devices are implemented for providing an adjustable resistance. According to one such implementation an adjustable resistive device includes a metal-oxide semiconductor (MOS) transistor having a gate, a drain, a source, and a body. First circuitry controls a resistance from drain to source by applying a gate voltage that is a function of a variable control input. Second circuitry adjusts a voltage at the body according to a drain voltage and a source voltage, whereby the resistance from drain to source is substantially linear for a given value of the variable control input and over a voltage range.
摘要翻译：实现了各种电路，方法和装置以提供可调电阻。根据一种这样的实施方案，可调电阻器件包括具有栅极，漏极，源极和主体的金属氧化物半导体（MOS）晶体管。第一电路通过施加作为可变控制输入的函数的栅极电压来控制从漏极到源极的电阻。第二电路根据漏极电压和源极电压来调节电压，由此对于给定的可变控制输入值和电压范围，漏极到源极的电阻基本上是线性的。

3. 发明申请

WO2005122391A1 VERFAHREN UND SCHALTUNGSANORDNUNG ZUR VERMEIDUNG VON STÖRIMPULSEN IM ZWISCHEN-FREQUENZSIGNAL SOWIE AM-EMPFÄNGER; ENTHALTEND EIN SOLCHES VERFAHREN BZW: EINE SOLCHE SCHALTUNGSANORDNUNG 审中-公开
标题翻译：方法与电路避免中频信号和接收器可能出现的干扰; 含有这种过程或：这样的电路
公开(公告)号：WO2005122391A1
公开(公告)日：2005-12-22
申请号：PCT/IB2005/051790
申请日：2005-06-02
申请人： PHILIPS INTELLECTUAL PROPERTY & STANDARDS GMBH , KONINKLIJKE PHILIPS ELECTRONICS N. V. , KOHSIEK, Cord-Heinrich
发明人： KOHSIEK, Cord-Heinrich
IPC分类号： H03D7/14
CPC分类号： H03D7/1425 , H03D7/1433 , H03D7/1458
摘要： Bei einem Verfahren und einer Schaltungsanordnung zur Vermeidung von Störimpulsen im Zwischenfrequenzsignal in einem einen Mischer enthaltenden AM-Empfänger, bei dem ein dem Mischer zugeführtes Hochfrequenzsignal beim Auftreten von Störungen ausgetastet wird, ist vorgesehen, dass während der Austastung des Hochfrequenzsignals ein für das Zwischenfrequenzsignal vorgesehenes Filter entdämpft wird.
摘要翻译：在一种方法和用于在含AM-接收器的混频器，其中提供给在干扰的发生混频器高频信号的信号被消隐中频信号预防干扰脉冲的电路装置，它提供了一种用于高频信号的消隐期间的中频信号滤波被deattenuated。

4. 发明公开

EP2039004A2 CIRCUIT FOR DETECTING THE DUTY CYCLE OF CLOCK SIGNALS 审中-公开
标题翻译：电路用于检测的占空比时钟信号
公开(公告)号：EP2039004A2
公开(公告)日：2009-03-25
申请号：EP07736050.1
申请日：2007-05-30
申请人： NXP B.V.
发明人： KOHSIEK, Cord-Heinrich
IPC分类号： H03K5/19 , G01R31/28
CPC分类号： H03K5/19 , H03K5/1252
摘要： A circuit (100) for detecting the duty cycle of clock signals comprises an oscillator (2) whose signal can be changed into a square-wave voltage in a gate (3). In order to obtain a simple construction of the circuit (100) with improved quality of the output signals a low-pass filter (3) is provided whose output signal is situated between 'low' and 'high'.

5. 发明授权

EP1348255B1 CIRCUIT ARRANGEMENT 有权
标题翻译：电路
公开(公告)号：EP1348255B1
公开(公告)日：2008-04-16
申请号：EP01987969.1
申请日：2001-10-17
申请人： NXP B.V.
发明人： KOHSIEK, Cord-Heinrich
IPC分类号： H03G7/00
摘要： In order to provide a circuit arrangement (100) for generating and amplifying a DC signal, referred to as level voltage, whose value is essentially proportional to the logarithm of the voltage amplitude of the input signal, the circuit arrangement comprising an amplifier circuit having at least two amplifier stages (10; 20; 30), it is proposed that: at least a differential amplifier stage (40), in particular non-negatively fed back, is arranged parallel to the last amplifier stage (30), particularly parallel to the collector circuits of the last amplifier stage (30); the differential amplifier stage (40) precedes at least a multiplier stage (50) for multiplying the output signals of the differential amplifier stage (40); for generating two differential amplifier output signals which are to be multiplied by each other, and alternatively to the differential amplifier (40), the collector currents of the transistors (36, 38) of the rectifier circuit (35) of the last amplifier stage (30) are used; and at least a current adder unit (80) is provided for adding the level voltage of the output signal of the multiplier stage (50) to the respective level voltage of the other amplifier stages.

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