专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP2665094A1 Tamper resistant IC 审中-公开
标题翻译： Manipulationssichere IC
公开(公告)号：EP2665094A1
公开(公告)日：2013-11-20
申请号：EP12168100.1
申请日：2012-05-15
申请人： NXP B.V.
发明人： Ostertun, Soenke , Ziesmann, Michael
IPC分类号： H01L23/58
CPC分类号： H03K19/003 , H01L21/306 , H01L23/576 , H01L2924/0002 , H01L2924/00
摘要： According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.
摘要翻译：根据本发明的一个方面，构想了一种集成电路，其包括物理不可克隆功能，其至少部分地实现在所述集成电路的钝化层中。根据本发明的另一方面，构思了用于制造集成电路的相应方法。根据本发明的另一方面，构思了包括所述类型的集成电路的电子设备。

2. 发明授权

EP2704063B1 Detection arrangement 有权
标题翻译：承认协议
公开(公告)号：EP2704063B1
公开(公告)日：2015-07-15
申请号：EP12182221.7
申请日：2012-08-29
申请人： NXP B.V.
发明人： Ostertun, Soenke , Garbe, Joachim Christoph Hans
IPC分类号： G06K19/073
CPC分类号： G06F21/60 , G06K19/07372

3. 发明公开

EP2713519A1 Electronic counter in non-volatile limited endurance memory 审中-公开
标题翻译： ElektronischerZähler在einemnichtflüchtigenSpeicher mit begrenzter Ausdauer
公开(公告)号：EP2713519A1
公开(公告)日：2014-04-02
申请号：EP12186356.7
申请日：2012-09-27
申请人： NXP B.V.
发明人： Feldhofer, Martin , Amtmann, Franz , Ostertun, Soenke , Da Conceicao, Alicia
IPC分类号： H03K21/40
CPC分类号： G06F12/00 , H03K21/403
摘要： An electronic counter comprising
- a sequence of memory cells, each memory cell being non-volatile and supporting a one state and a zero state, the counter being configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and
- increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter, the increment logic comprising programming increment logic and erasing increment logic, the increment logic being configured to alternate between a programming phase in which the programming increment logic advances the pattern, and an erasing phase in which the erasing increment logic advances the pattern, wherein
- the programming increment logic is configured to program a next cell of the sequence of non-volatile memory cells from a zero state to a one state, the program phase terminating when all memory cells of the sequence of memory cells are in the one state,
- the erasing increment logic is configured to erase a next cell of the sequence of non-volatile memory cells from a one state to a zero state, the erase phase terminating when all memory cells of the sequence of memory cells are in the zero state.
摘要翻译：一种电子计数器，包括：一系列存储器单元，每个存储器单元是非易失性的并且支持一种状态和零状态，所述计数器被配置为将所述计数器的当前计数状态的至少一部分表示为存储器单元序列的存储器单元中的一个和零个状态，以及 - 被配置为将一个和零个状态的模式提前到下一个模式的递增逻辑，以表示计数器的增量，该增量逻辑包括编程增量逻辑和擦除增量逻辑被配置为在编程增量逻辑推进模式的编程阶段与擦除增量逻辑使模式前进的擦除阶段之间交替，其中 - 编程增量逻辑被配置为对下一个非易失性存储器单元的序列的单元从零状态到一个状态，当序列的所有存储单元的序列存储器单元的存在处于一个状态， - 擦除增量逻辑被配置为将非易失性存储器单元序列中的下一个单元从一个状态擦除到零状态，擦除阶段在所有存储单元的所有存储器单元存储器单元的序列处于零状态。

4. 发明公开

EP4390928A1 NON-VOLATILE MEMORY SYSTEM WITH SECURE DETECTION OF VIRGIN MEMORY CELLS 审中-公开
公开(公告)号：EP4390928A1
公开(公告)日：2024-06-26
申请号：EP23216846.8
申请日：2023-12-14
申请人： NXP B.V.
发明人： Ostertun, Soenke
IPC分类号： G11C7/20 , G11C7/24 , G11C29/50
CPC分类号： G11C2013/008320130101 , G11C7/24 , G11C7/20 , G11C29/50008 , G11C2029/500220130101 , G11C29/50 , G11C2029/040720130101
摘要： In a non-volatile memory (NVM) system of a memory device, a memory controller connected to memory cell arrays of the NVM system is configured to perform the steps of selecting a memory cell to test, energizing a test circuit connected to the memory cell under a first biasing condition, reading a measurement of an electrical property of the memory cell, and determining, based on the measurement, whether the memory cell is formed or unformed. In embodiments, the system and method include protecting the test circuit from attack by validating the results of the testing. The memory controller is further configured to energize the test circuit under a second biasing condition that produces a known test result whether the memory cell is formed or unformed; if the result of the second test is not the expected result, the memory controller determines that the testing circuit is malfunctioning or under attack.

5. 发明公开

EP3023990A1 Multi independent page erase 审中-公开
标题翻译： MehrfachunabhängigeSeitenlöschung
公开(公告)号：EP3023990A1
公开(公告)日：2016-05-25
申请号：EP14194036.1
申请日：2014-11-20
申请人： NXP B.V.
发明人： Storms, Maurits , Ostertun, Soenke
IPC分类号： G11C16/16
CPC分类号： G11C16/16
摘要： Embodiments of a system (200) to perform an erase operation on a memory device (120) include a storage device (134) and a flash memory device including a flash memory controller (128). The storage device (134) is configured to store a list of multiple pages to be erased from a flash memory device. The list includes two or more independent pages residing on different erase blocks on the flash memory device. The flash memory is configured to select at least two or more independent pages on the list of multiple pages to be erased from the flash memory device and perform an erase operation erasing the selected at least two or more independent pages on the list of multiple pages to be erased from the flash memory device.
摘要翻译：在存储设备（120）上执行擦除操作的系统（200）的实施例包括存储设备（134）和包括闪速存储器控制器（128）的闪存设备。存储设备（134）被配置为存储要从闪存设备擦除的多个页面的列表。该列表包括驻留在闪存设备上的不同擦除块上的两个或多个独立页面。闪速存储器被配置为从闪速存储器设备中选择要擦除的多个页面上的至少两个或更多个独立页面，并执行擦除在多个页面列表上所选择的至少两个或更多个独立页面的擦除操作从闪存设备中擦除。

6. 发明授权

EP3107106B1 VOLTAGE DRIVER CIRCUIT FOR FLASH MEMORY DEVICES 有权
公开(公告)号：EP3107106B1
公开(公告)日：2018-10-31
申请号：EP15172890.4
申请日：2015-06-19
申请人： NXP B.V.
发明人： Storms, Maurits , Ostertun, Soenke , Cevela, Frantisek
IPC分类号： G11C16/30 , G11C16/08 , H03K3/356 , G11C5/14 , G11C8/08
CPC分类号： H03K3/356182 , G11C5/14 , G11C5/147 , G11C8/08 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , H02M3/07 , H03K3/35613
摘要： There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply terminal (122), a second voltage supply terminal (124), and a first biasing voltage output terminal (126), wherein the first switching element (N11, N12) is adapted to connect the first biasing voltage output terminal (126) to the first voltage supply terminal (122) in dependency of the voltage at the first latch output terminal (114), and wherein the second switching element (N13) is adapted to connect the first biasing voltage output terminal (126) to the second voltage supply terminal (124) in dependency of the voltage at the second latch output terminal (115), and (c) a second output stage (130) comprising a third switching element (N21), a fourth switching element (N22), a third voltage supply terminal (132), a fourth voltage supply terminal (134), and a second biasing voltage output terminal (136), wherein the third switching element (N21) is adapted to connect the second biasing voltage output terminal (136) to the third voltage supply terminal (132) in dependency of the voltage at the first latch output terminal (114), and wherein the fourth switching element (N22) is adapted to connect the second biasing voltage output terminal (136) to the fourth voltage supply terminal (134) in dependency of the voltage at the second latch output terminal (115).There is also described a memory system and a method of operating the driver circuit.

7. 发明公开

EP3107106A1 VOLTAGE DRIVER CIRCUIT FOR FLASH MEMORY DEVICES 有权
标题翻译： SPANNUNGSTREIBERSCHALTUNGFÜRFLASH SPEICHERVORRICHTUNGEN
公开(公告)号：EP3107106A1
公开(公告)日：2016-12-21
申请号：EP15172890.4
申请日：2015-06-19
申请人： NXP B.V.
发明人： Storms, Maurits , Ostertun, Soenke , Cevela, Frantisek
IPC分类号： G11C16/08 , G11C16/30 , H03K3/356
CPC分类号： H03K3/356182 , G11C5/14 , G11C5/147 , G11C8/08 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , H02M3/07 , H03K3/35613
摘要： There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply terminal (122), a second voltage supply terminal (124), and a first biasing voltage output terminal (126), wherein the first switching element (N11, N12) is adapted to connect the first biasing voltage output terminal (126) to the first voltage supply terminal (122) in dependency of the voltage at the first latch output terminal (114), and wherein the second switching element (N13) is adapted to connect the first biasing voltage output terminal (126) to the second voltage supply terminal (124) in dependency of the voltage at the second latch output terminal (115), and (c) a second output stage (130) comprising a third switching element (N21), a fourth switching element (N22), a third voltage supply terminal (132), a fourth voltage supply terminal (134), and a second biasing voltage output terminal (136), wherein the third switching element (N21) is adapted to connect the second biasing voltage output terminal (136) to the third voltage supply terminal (132) in dependency of the voltage at the first latch output terminal (114), and wherein the fourth switching element (N22) is adapted to connect the second biasing voltage output terminal (136) to the fourth voltage supply terminal (134) in dependency of the voltage at the second latch output terminal (115).There is also described a memory system and a method of operating the driver circuit.
摘要翻译：描述了一种用于向闪速存储器件提供偏置电压的驱动器电路（100），该驱动电路包括（a）电平移位器锁存器（110），包括第一锁存器输入端（111），第一锁存控制端（112）），锁存电压源端子（113），第一锁存器输出端子（114）和第二锁存器输出端子（115），其中电平转换器锁存器（110）适于根据第一锁存器输入端子（111），第一锁存器输出端子（114）处的第一电压和第二电压中的一个以及第二锁存器输出端子（115）处的第一电压和第二电压中的另一个，其中，第一电压取决于施加到锁存电压电源端子（113）的电压，并且第二电压取决于施加到第一锁存器控制端子（112）的电压，（b）第一输出级（120）包括第一开关元件（N11，N12），第二开关元件（N13），第一电压供给端子（122），第二电压供给端子（124）和第一偏置电压输出端子（126），其中第一开关元件（N11，N12）适于将第一偏置电压输出端子 126）根据第一锁存器输出端子（114）处的电压到第一电压供应端子（122），并且其中第二开关元件（N13）适于将第一偏置电压输出端子（126）连接到第二电压供给端子（124），其依赖于第二锁存器输出端子（115）处的电压，以及（c）第二输出级（130），包括第三开关元件（N21），第四开关元件（N22）第三电压供给端子（132），第四电压供给端子（134）和第二偏置电压输出端子（136），其中第三开关元件（N21）适于连接第二偏置电压输出端子（136）到第三电压供应端子（132）在第一锁存器输出端子（114）处的电压的下降，并且其中第四开关元件（N22）适于根据电压将第二偏置电压输出端子（136）连接到第四电压供应端子（134）在第二闩锁输出端子（115）处。还描述了一种存储器系统和操作驱动器电路的方法。

8. 发明公开

EP2704063A1 Detection arrangement 有权
标题翻译： Erkennungsanordnung
公开(公告)号：EP2704063A1
公开(公告)日：2014-03-05
申请号：EP12182221.7
申请日：2012-08-29
申请人： NXP B.V.
发明人： Ostertun, Soenke , Garbe, Joachim Christoph Hans
IPC分类号： G06K19/073
CPC分类号： G06F21/60 , G06K19/07372
摘要： There is provided a detection arrangement for detecting an attack to internal signals in a semiconductor device. The detection arrangement comprises a first input terminal, a second input terminal, and a comparison unit. The first input terminal is adapted to receive a first signal being indicative for a signal at a first stage of a driver of the semiconductor device, the driver being capable to drive signals internally to the semiconductor device. The second input terminal is adapted to receive a second signal being indicative for a signal at a second stage of the driver of the semiconductor device. The comparison unit is adapted to compare the first signal and the second signal and to determine a time period during which the signals are equal, wherein the determined time period is indicative for a potential attack, if the determined time period is above a predefined threshold.
摘要翻译：提供了用于检测对半导体器件中的内部信号的攻击的检测装置。检测装置包括第一输入端子，第二输入端子和比较单元。第一输入端子适于接收指示半导体器件的驱动器的第一级处的信号的第一信号，该驱动器能够将信号内部驱动到半导体器件。第二输入端适于接收在半导体器件的驱动器的第二级指示信号的第二信号。所述比较单元适于比较所述第一信号和所述第二信号，并且确定所述信号相等的时间段，其中如果所确定的时间段高于预定阈值，则所述确定的时间段指示潜在的攻击。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式