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1. 发明申请

WO2007045961A1 BLOCK SERIAL PIPELINED LAYERED DECODING ARCHITECTURE FOR STRUCTURED LOW-DENSITY PARITY-CHECK (LDPC) CODES 审中-公开
标题翻译：用于结构化低密度奇偶校验（LDPC）编码的块式串行管道层级解码架构
公开(公告)号：WO2007045961A1
公开(公告)日：2007-04-26
申请号：PCT/IB2006/002883
申请日：2006-10-16
申请人： NOKIA CORPORATION , BHATT, Tejas , SUNDARAMURTHY, Vishwas , STOLPMAN, Victor , MCCAIN, Dennis
发明人： BHATT, Tejas , SUNDARAMURTHY, Vishwas , STOLPMAN, Victor , MCCAIN, Dennis
IPC分类号： H03M13/00 , H03M13/45 , G06F11/00 , H04L27/00
CPC分类号： H03M13/1145 , H03M13/1111 , H03M13/1117 , H03M13/1122 , H03M13/1131
摘要： An error correction decoder for block serial pipelined layered decoding of block codes includes primary and mirror memories that are each capable of storing log-likelihood ratios (LLRs) for one or more iterations of an iterative decoding technique. The decoder also includes a plurality of elements capable of processing, for one or more iterations, one or more layers of a parity-check matrix. The elements include an iterative decoder element capable of calculating, for one or more iterations or layers, a LLR adjustment based upon the LLR for a previous iteration/layer, the LLR for the previous iteration/layer being read from the primary memory. The decoder further includes a summation element capable of reading the LLR for the previous iteration/layer from the mirror memory, and calculating the LLR for the iteration/layer based upon the LLR adjustment for the iteration/layer and the previous iteration/layer LLR for the previous iteration/layer.
摘要翻译：用于块码的块串行流水线分层解码的纠错解码器包括主存储器和镜像存储器，每个存储器能够存储用于迭代解码技术的一次或多次迭代的对数似然比（LLR）。解码器还包括能够对一个或多个迭代处理奇偶校验矩阵的一个或多个层的多个元件。这些元件包括能够针对一个或多个迭代或层来计算基于先前迭代/层的LLR的LLR调整的迭代解码器元件，从主存储器读取先前迭代/层的LLR。解码器还包括能够从镜像存储器读取先前迭代/层的LLR并且基于迭代/层和先前的迭代/层LLR的LLR调整来计算迭代/层的LLR的求和元素，用于以前的迭代/层。

2. 发明申请

WO2007029114A3 SYSTEM, TRANSMITTER, RECEIVER, METHOD, AND COMPUTER PROGRAM PRODUCT FOR STRUCTURED INTERLEAVED ZIGZAG CODING 审中-公开
公开(公告)号：WO2007029114A3
公开(公告)日：2007-03-15
申请号：PCT/IB2006/002537
申请日：2006-08-30
申请人： NOKIA CORPORATION , BHATT, Tejas , STOLPMAN, Victor , MCCAIN, Dennis
发明人： BHATT, Tejas , STOLPMAN, Victor , MCCAIN, Dennis
IPC分类号： H03M13/27 , H03M13/29
摘要： A system, transmitter, receiver, method, and computer program product are provided in which a plurality of structured interleavers permute data bits arranged in a data bit matrix for Zigzag encoding. For each interleaver, the data bits in each column of the data bit matrix are cyclically shifted, with the amount of the shift being predefined and different for each column. In addition to the cycle shift, each column may be bit reverse ordered, and entire columns may be swapped. The interleaved data bit matrix may then be encoded using a Zigzag encoder to generate parity bits that may be transmitted, along with the data bits, from a transmitter to a receiver where the data may be iteratively decoded.

3. 发明申请

WO2007138453A2 METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT PROVIDING SYNCHRONIZATION FOR OFDMA DOWNLINK SIGNAL 审中-公开
标题翻译：方法，提供OFDMA下行链路信号同步的装置和计算机程序产品
公开(公告)号：WO2007138453A2
公开(公告)日：2007-12-06
申请号：PCT/IB2007/001405
申请日：2007-05-29
申请人： NOKIA CORPORATION , NOKIA INC. , BHATT, Tejas , SUNDARAMURTHY, Vishwas , ZHANG, Jianzhong , MCCAIN, Dennis
发明人： BHATT, Tejas , SUNDARAMURTHY, Vishwas , ZHANG, Jianzhong , MCCAIN, Dennis
IPC分类号： H04L27/26
CPC分类号： H04L27/2656 , H04L27/2659 , H04L27/266 , H04L27/2662 , H04L27/2675 , H04L27/2678
摘要： Disclosed is a method, a computer program product and a device that includes a receiver for receiving a downlink signal transmitted into a cell. The receiver is operable to obtain time, carrier frequency and cell-specific preamble synchronization to the received signal and includes a plurality of synchronization units that include a first detector to detect a frame boundary using preamble delay correlation; a second detector to detect the frame boundary with greater precision using a conjugate symmetry property over a region identified by the first detector; a cyclic prefix correlator to resolve symbol boundary repetition; an estimator, using the cyclic prefix, to estimate and correct a fractional carrier frequency offset; an operator to perform a Fast Fourier Transform of an identified preamble symbol and a frequency domain cross-correlator to identify cell-specific preamble sequences and an integer frequency offset in sub-carrier spacing. The transmitted signal may be a downlink signal transmitted into the cell from a base station that is compatible with IEEE 802.16e (WiMAX).
摘要翻译：公开了一种方法，计算机程序产品和设备，其包括用于接收发送到小区中的下行链路信号的接收机。接收机可操作以获得对接收信号的时间，载波频率和小区特定前导码同步，并且包括多个同步单元，其包括使用前导延迟相关来检测帧边界的第一检测器; 第二检测器，使用在由第一检测器识别的区域上的共轭对称性检测更高精度的帧边界; 用于解析符号边界重复的循环前缀相关器; 使用循环前缀的估计器来估计和校正分数载波频率偏移; 执行所识别的前导码符号的快速傅立叶变换和频域交叉相关器以识别小区特定前导码序列和子载波间隔中的整数频率偏移的运算符。所发送的信号可以是从与IEEE 802.16e（WiMAX）兼容的基站发送到小区的下行链路信号。

4. 发明申请

WO2006067566A2 A WEIGHTED AUTOCORRELATION METHOD FOR DOWNLINK CDMA LMMSE EQUALIZERS 审中-公开
标题翻译：下行链路CDMA LMMSE均衡器的加权自相关法
公开(公告)号：WO2006067566A2
公开(公告)日：2006-06-29
申请号：PCT/IB2005/003658
申请日：2005-12-02
申请人： NOKIA CORPORATION , NOKIA, INC. , NGUYEN, Hoang , ZHANG, Jianzhong , GUO, Yuanbin , MCCAIN, Dennis , DOWLING, Joe
发明人： NGUYEN, Hoang , ZHANG, Jianzhong , GUO, Yuanbin , MCCAIN, Dennis , DOWLING, Joe
CPC分类号： H04B1/71052 , H04B1/71055
摘要： Receiving downlink CDMA signals in a fast-fading environment is facilitated at higher receiver velocities by updating the block-adaptive linear minimum mean square error (LMMSE) downlink CDMA equalizer. The autocorrelation matrix of the observed data is updated by passing block-wise autocorrelation slides through a-filter. Each autocorrelation slide is an autocorrelation matrix estimated from a short block of observed data over which the channel can be considered constant. This method achieves a reliable estimate for the autocorrelation matrix when the block size must be small to ensure that the block-wise stationarity assumption holds in cases of fast fading channels. In addition, small block sizes make it possible to satisfy the equalizer delay constraint imposed by hardware and certain voice transmission standards such as CDMA2000 1X where demodulated data must be delivered within only several symbol periods of the signal arrival time. Preliminary simulation results obtained under the 1X standard show that the proposed method outperforms the Rake receiver and the ordinary block LMMSE equalizer in the presence of filtering delay. The improvement over the ordinary block LMMSE equalizer: is substantial in cases of high mobility.
摘要翻译：通过更新块自适应线性最小均方误差（LMMSE）下行链路CDMA均衡器，在快速衰落环境中接收下行链路CDMA信号在更高的接收机速度下被促进。观察数据的自相关矩阵通过将逐块自相关幻灯片传递通过滤波器来更新。每个自相关幻灯片是一个自相关矩阵，通过观察数据的短块估计，通道可以被视为常量。该方法在块大小必须很小时对自相关矩阵实现可靠估计，以确保在快衰落信道情况下块分段平稳假设成立。另外，小块大小可以满足硬件和某些语音传输标准（如CDMA2000 1X）所施加的均衡器延迟约束，其中解调数据必须在信号到达时间的几个符号周期内传送。在1X标准下获得的初步仿真结果表明，所提出的方法在存在滤波延迟的情况下优于Rake接收机和普通块LMMSE均衡器。对于普通模块LMMSE均衡器的改进：在高移动性的情况下非常重要。

5. 发明申请

WO2006056837A1 REDUCED PARALLEL AND PIPELINED HIGH-ORDER MIMO LMMSE RECEIVER ARCHITECTURE 审中-公开
标题翻译：减少的并行和流水线高阶MIMO LMMSE接收器架构
公开(公告)号：WO2006056837A1
公开(公告)日：2006-06-01
申请号：PCT/IB2005/003304
申请日：2005-11-04
申请人： NOKIA CORPORATION , NOKIA INC. , GUO, Yuanbin , ZHANG, Jianzhong , MCCAIN, Dennis , CAVALLARO, Joseph, R.
发明人： GUO, Yuanbin , ZHANG, Jianzhong , MCCAIN, Dennis , CAVALLARO, Joseph, R.
IPC分类号： H04L27/01 , H04B1/707
CPC分类号： H04L25/03038 , H04B1/71055 , H04L25/0204 , H04L25/021 , H04L25/0242 , H04L25/0328 , H04L2025/03375 , H04L2025/03426 , H04L2025/03477 , H04L2025/03605
摘要： Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size NxN with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2x2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4x4 matrices are partitioned into 2x2 block sub-matrices, inverted, and rebuilt into a 4x4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.
摘要翻译：公开了一种LMMSE接收机，其恢复在N个接收天线上接收的扩频信号的下行链路信道中的扩频码的正交性。基于FFT的码片均衡器抽头求解器将现有技术的直接矩阵求逆缩减为具有接收天线的维度的尺寸为N×N的一些子矩阵的逆矩阵，并且最有效地将矩阵求逆减小到不大于2×2。在传统的快速傅立叶变换方法中，通过厄米特优化到子矩阵和树修剪的逆，复杂度进一步降低。对于具有双重过采样的N = 4或N = 2的接收机，所得到的4×4矩阵被划分成2×2块子矩阵，反转并重建为4×4矩阵。通用计算被发现并且重复计算被消除以提高效率。通用设计架构来源于特殊设计模块，以消除复杂操作中的冗余。最佳的结构是并行和流水线的。

6. 发明申请

WO2006056836A1 FFT ACCELERATED ITERATIVE MIMO EQUALIZER RECEIVER ARCHITECTURE 审中-公开
标题翻译： FFT加速迭代MIMO均衡器接收机架构
公开(公告)号：WO2006056836A1
公开(公告)日：2006-06-01
申请号：PCT/IB2005/003294
申请日：2005-11-04
申请人： NOKIA CORPORATION , NOKIA, INC. , GUO, Yuanbin , MCCAIN, Dennis , CAVALLARO, Joseph, R.
发明人： GUO, Yuanbin , MCCAIN, Dennis , CAVALLARO, Joseph, R.
IPC分类号： H04L27/01 , H04B1/707
CPC分类号： H04L25/03044 , H04L2025/03426 , H04L2025/03643
摘要： A receiver, such as a CDMA MIMO receiver, includes a LMMSE-based chip-level equalizer constructed so as to implement a FFT accelerated iterative algorithm having a complexity of order O(Nlog 2 (N)) , where N is the dimension of a covariance matrix. The equalizer uses one of an overlap-save or an overlap-add FFT architecture.
摘要翻译：诸如CDMA MIMO接收机的接收机包括基于LMMSE的码片级均衡器，其被构造为实现具有阶数O（Nlog）的复杂度的FFT加速迭代算法

7. 发明申请

WO2006090278A1 SYSTEM, APPARATUS, AND METHOD FOR ADAPTIVE WEIGHTED INTERFERENCE CANCELLATION USING PARALLEL RESIDUE COMPENSATION 审中-公开
标题翻译：使用并行残差补偿的自适应加权干扰消除的系统，装置和方法
公开(公告)号：WO2006090278A1
公开(公告)日：2006-08-31
申请号：PCT/IB2006/000515
申请日：2006-02-20
申请人： NOKIA CORPORATION , NOKIA, INC.
发明人： GUO, Yuanbin , MCCAIN, Dennis , CAVALLARO, Joseph, R.
IPC分类号： H04B1/707
CPC分类号： H04B1/71075 , H04B2001/71077 , H04B2201/70707
摘要： A system, apparatus and method for a multi-stage Parallel Residue Compensation (PRC) receiver for enhanced suppression of the Multiple Access Interference (MAI) in Code Division Multiple Access (CDMA) systems. The accuracy of the interference estimation is improved with a set of weights computed from an adaptive Normalized Least Mean Square (NLMS) algorithm. In order to reduce complexity, the commonality of the multi-code processing is extracted and used to derive a structure of PRC to avoid direct interference cancellation. The derived PRC structure reduces the interference cancellation architecture from a complexity that is proportional to the square of the number of users to a complexity that is linear with respect to the number of users. The complexity is further reduced by replacing dedicated multiplier circuits with simple combinational logic.
摘要翻译：一种用于增强抑制码分多址（CDMA）系统中的多址干扰（MAI）的多级并行残差补偿（PRC）接收机的系统，装置和方法。通过从自适应归一化最小二乘法（NLMS）算法计算的一组权重，改善了干扰估计的准确性。为了降低复杂度，提取多码处理的通用性，并用于导出PRC的结构，以避免直接的干扰消除。导出的PRC结构从与用户数量的平方成正比于与用户数量相关的复杂度的复杂度降低了干扰消除架构。通过用简单的组合逻辑替换专用乘法电路，进一步降低了复杂度。

8. 发明公开

EP1815655A1 REDUCED PARALLEL AND PIPELINED HIGH-ORDER MIMO LMMSE RECEIVER ARCHITECTURE 审中-公开
标题翻译：简化并行与管道MIMO LMMSE接收器架构高阶
公开(公告)号：EP1815655A1
公开(公告)日：2007-08-08
申请号：EP05802365.6
申请日：2005-11-04
申请人： Nokia Corporation
发明人： GUO, Yuanbin , ZHANG, Jianzhong , MCCAIN, Dennis , CAVALLARO, Joseph, R.
IPC分类号： H04L27/01 , H04B1/707
CPC分类号： H04L25/03038 , H04B1/71055 , H04L25/0204 , H04L25/021 , H04L25/0242 , H04L25/0328 , H04L2025/03375 , H04L2025/03426 , H04L2025/03477 , H04L2025/03605
摘要： Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size NxN with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2x2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4x4 matrices are partitioned into 2x2 block sub-matrices, inverted, and rebuilt into a 4x4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.

9. 发明公开

EP1829233A2 A WEIGHTED AUTOCORRELATION METHOD FOR DOWNLINK CDMA LMMSE EQUALIZERS 审中-公开
标题翻译：加权自相关法DOWN RANGE CDMA LMMSE均衡器
公开(公告)号：EP1829233A2
公开(公告)日：2007-09-05
申请号：EP05810389.6
申请日：2005-12-02
申请人： Nokia Corporation
发明人： NGUYEN, Hoang , ZHANG, Jianzhong , GUO, Yuanbin , MCCAIN, Dennis , DOWLING, Joe
IPC分类号： H04B1/707 , H04L25/03
CPC分类号： H04B1/71052 , H04B1/71055
摘要： Receiving downlink CDMA signals in a fast-fading environment is facilitated at higher receiver velocities by updating the block-adaptive linear minimum mean square error (LMMSE) downlink CDMA equalizer. The autocorrelation matrix of the observed data is updated by passing block-wise autocorrelation slides through a-filter. Each autocorrelation slide is an autocorrelation matrix estimated from a short block of observed data over which the channel can be considered constant. This method achieves a reliable estimate for the autocorrelation matrix when the block size must be small to ensure that the block-wise stationarity assumption holds in cases of fast fading channels. In addition, small block sizes make it possible to satisfy the equalizer delay constraint imposed by hardware and certain voice transmission standards such as CDMA2000 1X where demodulated data must be delivered within only several symbol periods of the signal arrival time. Preliminary simulation results obtained under the 1X standard show that the proposed method outperforms the Rake receiver and the ordinary block LMMSE equalizer in the presence of filtering delay. The improvement over the ordinary block LMMSE equalizer: is substantial in cases of high mobility.

10. 发明公开

EP1851869A1 SYSTEM, APPARATUS, AND METHOD FOR ADAPTIVE WEIGHTED INTERFERENCE CANCELLATION USING PARALLEL RESIDUE COMPENSATION 审中-公开
标题翻译：系统，设备和方法自适应加权干扰消除使用并行REST补偿
公开(公告)号：EP1851869A1
公开(公告)日：2007-11-07
申请号：EP06710523.9
申请日：2006-02-20
申请人： Nokia Corporation
发明人： GUO, Yuanbin , MCCAIN, Dennis , CAVALLARO, Joseph, R.,
IPC分类号： H04B1/707
CPC分类号： H04B1/71075 , H04B2001/71077 , H04B2201/70707
摘要： A system, apparatus and method for a multi-stage Parallel Residue Compensation (PRC) receiver for enhanced suppression of the Multiple Access Interference (MAI) in Code Division Multiple Access (CDMA) systems. The accuracy of the interference estimation is improved with a set of weights computed from an adaptive Normalized Least Mean Square (NLMS) algorithm. In order to reduce complexity, the commonality of the multi-code processing is extracted and used to derive a structure of PRC to avoid direct interference cancellation. The derived PRC structure reduces the interference cancellation architecture from a complexity that is proportional to the square of the number of users to a complexity that is linear with respect to the number of users. The complexity is further reduced by replacing dedicated multiplier circuits with simple combinational logic.
摘要翻译：对于多级的系统，装置和方法对于平行于码分多址（CDMA）系统中的多址干扰（MAI）的增强的抑制残留补偿（PRC）接收机。干扰估计的准确度与一组从算法来计算权重的改进，以自适应归一化最小均方（NLMS）。为了减少复杂性，多码处理的共同性被提取并用于导出PRC的结构，以避免直接干扰消除。中华人民共和国衍生结构减少了从一个复杂的干扰消除体系结构所做的是正比于用户在复杂的数目的平方所做的是相对于用户的数量线性。复杂性是通过用简单的组合逻辑替代此外专用乘法器电路减小。

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