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1. 发明申请

WO2012052909A1 METHOD AND APPARATUS FOR PROVIDING PORTABILITY OF PARTIALLY ACCELERATED SIGNAL PROCESSING APPLICATIONS 审中-公开
标题翻译：提供部分加速信号处理应用可移植性的方法与装置
公开(公告)号：WO2012052909A1
公开(公告)日：2012-04-26
申请号：PCT/IB2011/054602
申请日：2011-10-17
申请人： NOKIA CORPORATION , BERG, Heikki Ilmari , HIRVOLA, Harri , ZETTERMAN, Tommi Juhani , RAISKILA, Kalle August
发明人： BERG, Heikki Ilmari , HIRVOLA, Harri , ZETTERMAN, Tommi Juhani , RAISKILA, Kalle August
IPC分类号： G06F9/45
CPC分类号： G06F9/44547
摘要： A method for providing portability of partially accelerated signal processing applications may include receiving target information descriptive of accelerated function availability of a target hardware platform, receiving source code for an application and defining functions associated with the application, at least one of the functions being capable of accelerated implementation in the target hardware platform, and causing compiling of an executable code including either an at least partially hardware accelerated implementation or a processor-based implementation based on the target information. A corresponding apparatus and computer program product are also provided.
摘要翻译：用于提供部分加速信号处理应用的可移植性的方法可以包括：接收描述目标硬件平台的加速功能可用性的目标信息，接收应用的源代码和定义与应用相关联的功能，所述功能中的至少一个能够在目标硬件平台中加速实现，并且导致基于目标信息编译包括至少部分硬件加速实现或基于处理器的实现的可执行代码。还提供了相应的装置和计算机程序产品。

2. 发明申请

WO2013121085A3 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR INTER-CORE COMMUNICATION IN MULTI-CORE PROCESSORS 审中-公开
公开(公告)号：WO2013121085A3
公开(公告)日：2013-08-22
申请号：PCT/FI2013/050088
申请日：2013-01-28
申请人： NOKIA CORPORATION
发明人： ZETTERMAN, Tommi Juhani , RAISKILA, Kalle August , HIRVOLA, Harri
IPC分类号： G06F12/08 , G06F13/362 , G06F9/38
摘要： Method, apparatus, and computer program product embodiments of the invention are disclosed for efficient communication between processor units in a multi-core processor integrated circuit architecture. In example embodiments of the invention, a method comprises: storing with a shared inter-core communication unit in a multi-core processor, first data produced by a producer processor core, in a first token memory located at a first memory address of a memory address space; and connecting with the shared inter-core communication unit, the first token memory to a consumer processor core of the multi-core processor, to load the first data from the first token memory into the consumer processor core, in response to a first-type command from the producer processor core.

3. 发明申请

WO2014202825A1 MICROPROCESSOR APPARATUS 审中-公开
标题翻译：微处理器
公开(公告)号：WO2014202825A1
公开(公告)日：2014-12-24
申请号：PCT/FI2013/050679
申请日：2013-06-20
申请人： NOKIA CORPORATION
发明人： ZETTERMAN, Tommi , HIRVOLA, Harri
IPC分类号： G06F9/38 , G06F9/30 , G06F13/16
CPC分类号： G06F15/7892 , G06F8/447
摘要： A heterogeneous multi-core processor is disclosed which comprises a controller, memory in the formof register files, as well as a local and a global memory, and a plurality of functional units (FUs). The FUs are transport-triggered type units which compute a particular algorithm using a particular data format (e.g. integer or floating point, 8-bit, 16-bit etc.) in response to a move or transfer instruction received at a triggering socket. The controller is configured to compile and execute different kernels in sequence using a Single Instruction Multiple Thread (SIMT) programming paradigm for efficient parallel processing. The controller is further configured to identify the computational and data format requirements of the current kernel, and to configure the core to support the requirements by means of connecting appropriate ones of the FUs to the controller and memory. In the event that a core storing data for use by the current kernel is not itself able to support the kernel's requirements, inter-core communications take place so that an alternative core can process the kernel.
摘要翻译：公开了一种异构多核处理器，其包括控制器，寄存器文件形式的存储器，以及本地和全局存储器以及多个功能单元（FU）。 FU是传输触发型单元，其响应于在触发插座处接收的移动或传送指令，使用特定数据格式（例如，整数或浮点，8位，16位等）计算特定算法。控制器被配置为使用单指令多线程（SIMT）编程范例来顺序编译和执行不同的内核，以实现高效的并行处理。控制器还被配置为识别当前内核的计算和数据格式要求，并且通过将适当的FU连接到控制器和存储器来配置核来支持要求。如果存储当前内核使用的数据的内核本身本身不能支持内核的要求，则会发生核心间通信，以便替代核心可以处理内核。

4. 发明申请

WO2013186430A3 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR FAST CONTEXT SWITCHING OF APPLICATION SPECIFIC PROCESSORS 审中-公开
公开(公告)号：WO2013186430A3
公开(公告)日：2013-12-19
申请号：PCT/FI2013/050555
申请日：2013-05-22
申请人： NOKIA CORPORATION
发明人： ZETTERMAN, Tommi Juhani , HIRVOLA, Harri
IPC分类号： G06F9/46 , G06F9/38 , G06F9/30 , G06T1/20
摘要： Embodiments of the invention enable fast context switching of application specific processors having functional units with an architecturally visible state. In example embodiments, a processor allocates memory space to store two process control blocks for two active tasks to be performed by the processor comprising one or more custom functional units having a respective processing state not accessible by the processor. A memory controller stores the processing state of the custom functional units currently running a first active task, in a first process control block, in response to a preemptive task switch requirement. The memory controller loads a second processing state of the custom functional units for a second active task, from a second process control block in the memory, in response to the preemptive task switch requirement. The processor may then perform the second active task, based on the second processing state loaded into the custom functional units.

5. 发明公开

EP2815322A2 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR INTER-CORE COMMUNICATION IN MULTI-CORE PROCESSORS 审中-公开
标题翻译：方法，设备和计算机程序产品为多核心处理器内核之间的通信
公开(公告)号：EP2815322A2
公开(公告)日：2014-12-24
申请号：EP13748915.9
申请日：2013-01-28
申请人： Nokia Corporation
发明人： ZETTERMAN, Tommi Juhani , RAISKILA, Kalle August , HIRVOLA, Harri
IPC分类号： G06F12/08 , G06F13/362 , G06F9/38
CPC分类号： G06F12/084 , G06F9/544 , G06F12/0284 , G06F12/0806 , G06F15/167 , Y02D10/13
摘要： Method, apparatus, and computer program product embodiments of the invention are disclosed for efficient communication between processor units in a multi-core processor integrated circuit architecture. In example embodiments of the invention, a method comprises: storing with a shared inter-core communication unit in a multi-core processor, first data produced by a producer processor core, in a first token memory located at a first memory address of a memory address space; and connecting with the shared inter-core communication unit, the first token memory to a consumer processor core of the multi-core processor, to load the first data from the first token memory into the consumer processor core, in response to a first-type command from the producer processor core.

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