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1. 发明专利

JPS55154841A COMMUNICATION CONTROL SYSTEM 失效
公开(公告)号：JPS55154841A
公开(公告)日：1980-12-02
申请号：JP11357279
申请日：1979-09-06
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： AKIYAMA AKIFUMI , KAMISAKA KIYUUICHI , FUKUOKA SHIGERU , ENDOU ISAO , TAKAHASHI HISASHI
IPC分类号： H04M15/00 , H04L1/16 , H04L1/18 , H04L29/08 , H04W28/04 , H04W76/02
摘要： PURPOSE:To make it possible to prevent repetitive operation securely by putting a timer into operation when a unit is actuated by an actuation control signal and by inhibiting it from being restarted in the operation of the timer afterward even on arrival of the control signal. CONSTITUTION:When unit B requests unit A to operate, sequence control part SCE2 sends an actuation request signal out from transmission part Tx2. On receiving this signal by reception part Rx1 of unit A, sequence control part SCE1 makes sure that timer T is not in operation and then actuates operation control part CE1 to perform requested operation while starting timer T by sending a response signal out from transmission part Tx1. Here, if the response signal would not reach unit B, unit B sends the actuation request signal again. Once unit A receives this signal by Rx1, SCE1 sends its response signal only from Tx1 to unit B without driving CE1 in case that timer T is in operation.

2. 发明专利

JPS56143757A PICTURE INFORMATION DISPLAY DEVICE 失效
公开(公告)号：JPS56143757A
公开(公告)日：1981-11-09
申请号：JP4771580
申请日：1980-04-10
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： FUKUOKA SHIGERU , YUUKI KANKOU , MATSUDA HIDEO
IPC分类号： H04N1/00 , H04N1/04 , H04N1/40
摘要： PURPOSE:To keep the secrecy of communication easily and to perform proper monitoring instantaneously by converting facsimile picture information into a normal composite video signal and by displaying the contents of the picture information on a television monitor. CONSTITUTION:Facsimile picture information inputted to line memory write control circuit 1 is written in line memory 2 at write control timing equivalent to the end of every line. Circuit 1 checks the agreement between write and read contents and when the both agree mutually, the contents are sent to data bus control circuit 3. The picture information inputted to circuit 3 has the fascimile synchronizing signal removed and is written in screen memory 4 according to a write address. The contents of memory 4 are read out at a read address and then edited into a normal composite video signal by video signal composing circuit 5, so that it will be sent out of video signal output circuit 6.

3. 发明专利

JPS56115958A LEVEL MEASURING DEVICE FOR FACSIMILE APPARATUS 失效
公开(公告)号：JPS56115958A
公开(公告)日：1981-09-11
申请号：JP1880280
申请日：1980-02-18
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： FUKUOKA SHIGERU , YUUKI KANKOU , MATSUDA HIDEO
IPC分类号： G01R19/04 , G01R19/165 , G01R19/25
摘要： PURPOSE:To make it possible to perform correctly a digital display by switching a range after holding a peak of level of the transmitting-and-receiving signals of facsimile store and convert device at each period in a short time. CONSTITUTION:The measured input signal from the connected circuit of the facsimile store and convert device is converted into the DC signal by a detector 3 through an attenuator for range conversion 1 and an amplifier 2 further to be given to the peak hold circuit 11 through a gate circuit 10 to be opened by the timing signal from the control circuit 7'. Said peak-held level is decided by a range decision comparator 6 whether it is in the input voltage range fixed by the dB converter 5 or not to regulate the attenuator 1 through the range counter 9. The pulse of the number corresponding to the decibel value from the dB converter 5 is given to the counter 8 and the range counter 9. Thereby it is made possible to perform a correct monitoring of the facsimile apparatus by correctly displaying the signal in a short repeated period.

4. 发明专利

JP2576270B2 失效
公开(公告)号：JP2576270B2
公开(公告)日：1997-01-29
申请号：JP18763590
申请日：1990-07-16
申请人： NIPPON ELECTRIC CO
发明人： FUKUOKA SHIGERU
IPC分类号： H04N1/32 , H04B7/15 , H04L1/16 , H04L29/08

5. 发明专利

JPH0622342B2 失效
公开(公告)号：JPH0622342B2
公开(公告)日：1994-03-23
申请号：JP25907686
申请日：1986-10-29
申请人： NIPPON ELECTRIC CO
发明人： FUKUOKA SHIGERU
IPC分类号： H04N1/00 , H04B7/15 , H04N7/20

6. 发明专利

JPS57132472A VIDEO INFORMATION DISPLAY CONTROLLER 失效
公开(公告)号：JPS57132472A
公开(公告)日：1982-08-16
申请号：JP1768981
申请日：1981-02-09
申请人： NIPPON ELECTRIC CO
发明人： FUKUOKA SHIGERU
IPC分类号： H04N1/00 , H04N1/04 , H04N1/40
摘要： PURPOSE:To achieve detailed display of facsimile video information and display keeping similarity with a transmission original, by providing a line memory, a picture memory, a similar address controlling circuit and a one-bit video signal synthesis circuit. CONSTITUTION:Facsimile video information is inputted to a line memory write- in controlling circuit 1 and written in a line memory 2. The video information per one line written in the memory 2 is written in a picture memory 4 via a data bus controlling circuit 3. The content of the memory 4 is read out so that the display to a display device is similar to a facsimile transmission original with a readout address generated at a similar address controlling circuit 17. For this readout jump scanning control of TV is made, and the signal is edited into a composite video signal by taking one dot as one spot at a one dot video signal synthesizing circuit 7 and transmitted from a video signal output circuit 6.

7. 发明专利

JPS58125953A AUTOMATIC REDUCING CIRCUIT OF COPY 失效
公开(公告)号：JPS58125953A
公开(公告)日：1983-07-27
申请号：JP742482
申请日：1982-01-22
申请人： NIPPON ELECTRIC CO
发明人： FUKUOKA SHIGERU
IPC分类号： H04N1/393 , H04N1/04 , H04N1/387
摘要： PURPOSE:To transmit faithfully the picture signals of a contracted original, by obtaining a sampling clock signal in the main scanning direction and a folded picture signal of the secondary scan with an output control of a picture element sampling indication circuit and the number of lines eliminating control circuit, respectively. CONSTITUTION:When an original picture is copied, a video clock signal (a) is supplied to a picture element sampling circuit 11 to the primary scanning direction. At the same time, a picture element sampling indicating circuit 12 receives a picture element sampling indicating signal (b) and a copy mode signal (f) and is driven in a copy mode. Then the circuit 11 has a counting operation by the control of the output of the circuit 12. The output of the circuit 12 is applied to a gate circuit 13 along with the count output of the circuit 11, and a sampling signal (d) is obtained from the gate output. In such a constitution, the output of the circuit 13 is set at a low level by an extent equivalent to a clock and every fixed period when the signal (b) is set at a low level. Thus the signal (d) is stopped. At the same time, a picture signal (c) is written to a line memory 14 also in the secondary scanning direction. Then the number of lines is deleted in the same ratio by number of the lines eliminating control circuit 15.

8. 发明专利

JP2576218B2 失效
公开(公告)号：JP2576218B2
公开(公告)日：1997-01-29
申请号：JP2295689
申请日：1989-01-31
申请人： NIPPON ELECTRIC CO
发明人： FUKUOKA SHIGERU
IPC分类号： H04N1/21 , H04L13/08 , H04N1/40 , H04N1/411

9. 发明专利

JPH0481906B2 失效
公开(公告)号：JPH0481906B2
公开(公告)日：1992-12-25
申请号：JP17602786
申请日：1986-07-25
申请人： NIPPON ELECTRIC CO
发明人： FUKUOKA SHIGERU
IPC分类号： H04L29/06 , H04L13/00 , H04N1/32

10. 发明专利

JPS60145762A FACSIMILE EQUIPMENT 失效
公开(公告)号：JPS60145762A
公开(公告)日：1985-08-01
申请号：JP216984
申请日：1984-01-10
申请人： NIPPON ELECTRIC CO
发明人： FUKUOKA SHIGERU
IPC分类号： H04N1/00
摘要： PURPOSE:To enable to transmit and receive dividing an original for destination by counting number of lines up to a line in the direction of main scanning printed on the original for destination and discriminating punctuation. CONSTITUTION:The original for destination is read by a reading circuit 1 by operation of an operating circuit 4, and coded by a coder decoder circuit 2. A line controlling circuit 7 measures number of lines up to a line L1 printed in the direction of main scanning, that is, the length from the first line of address data R1 to the last line of addresser data S1, and when this arrives at a regulating value, sends out a pause signal to a controlling circuit 3'. The controlling circuit 3', basing on above-mentioned pause signal, divides the original for destination to plural divisions and sends out to a circuit. Receiving side receives the transmitted signal dividing it according to the pause signal, and cuts recording paper automatically every time the pause signal is received.

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