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1. 发明专利

JPS53148927A TEST SYSTEM FOR MEMORY ADDRESS GROUP CIRCUITS 失效
公开(公告)号：JPS53148927A
公开(公告)日：1978-12-26
申请号：JP6318677
申请日：1977-06-01
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： KISHI SEISHICHI , OOMA TOSHIO
IPC分类号： G11C11/413 , G11C7/00 , G11C8/00 , G11C11/34 , G11C29/00 , G11C29/04 , G11C29/56
摘要： PURPOSE:To secure a test even for the address bit fault in ashort time without using any diagnosis circuit by reading out both the head and the final addresses and deciding the contents of the read out address to give a test to the address group circuits of the test unit.

2. 发明专利

JPS5330245A TEST METHOD FOR LOGICAL UNIT SYSTEM 失效
公开(公告)号：JPS5330245A
公开(公告)日：1978-03-22
申请号：JP10523476
申请日：1976-09-02
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： KISHI SEISHICHI , OONISHI NOBORU , OOTSU YOSHIKATSU , OOMA TOSHIO , KUMAGAI YUKIO
IPC分类号： G06F11/16 , G01R31/00 , G01R31/28 , G06F11/00 , G06F15/16 , G06F15/177
摘要： PURPOSE:To realize a test without any collation circuit available by flowing a test data once to each accessory unit and central control unit CC and receiving the data at CC. As a result, the test accuracy can be enhanced for the unit which contains a common circuit.

3. 发明专利

JPS5283043A PREVENTION DEVICE OF ERRONEOUS OPERATION 失效
公开(公告)号：JPS5283043A
公开(公告)日：1977-07-11
申请号：JP15903075
申请日：1975-12-29
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： TAGA KAZUYUKI , KISHI SEISHICHI , KAWASHIMA YOUICHI , TAJIMA KIYOHIDE , ANDOU TETSUYA
IPC分类号： G06F11/00
摘要： PURPOSE:To prevent the erroneous operation by installing the cover of the switch for the power supply switch stack and the switch for the power supply.

4. 发明专利

JPS5330246A DIAGNOSIS METHOD FOR LOGICAL UNIT SYSTEM 失效
公开(公告)号：JPS5330246A
公开(公告)日：1978-03-22
申请号：JP10523576
申请日：1976-09-02
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： KISHI SEISHICHI , OONISHI NOBORU , OOTSU YOSHIKATSU , OOMA TOSHIO , SUZUKI MASANORI
IPC分类号： G06F11/16 , G01R31/00 , G01R31/28 , G06F11/00 , G06F15/16 , G06F15/177
摘要： PURPOSE:To secure a high-accuracy diagnosis even in case a collation circuit is not available or a common circuit is available, by having an analyzation of the return data.

5. 发明专利

JPS5343441A TEST METHOD FOR IC MEMORY ELEMENT 失效
公开(公告)号：JPS5343441A
公开(公告)日：1978-04-19
申请号：JP11821576
申请日：1976-10-01
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： KISHI SEISHICHI , OONISHI NOBORU , KAWANOBE TADASHI , OOTSU YOSHIKATSU , DAIMA TOSHIO
IPC分类号： G06F11/22 , G11C11/413 , G11C29/10
摘要： PURPOSE:To realize a test method for an IC memory element using an inverting cell system, which can detect the fault of the address and data systems and also shorten the test time without receiving any influence of the element's physical structure.

6. 发明专利

JPS5245236A SYSTEM FOR CONTROLLING THE CHANGEEOVER OF UNITS WITH FAULT 失效
公开(公告)号：JPS5245236A
公开(公告)日：1977-04-09
申请号：JP12116875
申请日：1975-10-07
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , OKI ELECTRIC IND CO LTD , FUJITSU LTD
发明人： KISHI SEISHICHI , MOTOHASHI KENICHI , HAYASHI SHIGEO , TSUJIMURA ATSUHIKO , TEJIMA TOORU
IPC分类号： G06F11/20 , G06F11/00 , G06F13/00 , G06F15/16
摘要： PURPOSE:To minimize the lowering of function due to fault in central processors by enabling the fault change-over function of control units having hierarchy of information processing system through hardware mechanism only.

7. 发明专利

JPS5583858A TEST METHOD OF FLAT CABLE 失效
公开(公告)号：JPS5583858A
公开(公告)日：1980-06-24
申请号：JP15650578
申请日：1978-12-20
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： KISHI SEISHICHI , KAWAKAMI TAKASHI , OOTSU YOSHIKATSU , TOYAMA TSUGIO
IPC分类号： H01B13/00 , G01R31/02
摘要： PURPOSE:To test transmission errors by classifying signal line pairs into remainder classes of rule m in order of arrangement and giving a complementary relation between test data, which is sent to signal line pairs belonging to one remainder group, and test data which is sent to all other signal line pairs. CONSTITUTION:8 Signals X0-X7 are stored in one flat cable, and 8 flat cables FC0-FC7 are used to transmit and receive signals between units. Data D and D are assigned to respective signal line pairs and have a complementary relation for each other. Signal line pairs are classified in order of arrangement with rule 5, and data D is sent to signal line pairs of remainder class 0, and data D having a complementary relation for D is sent to other signal line pairs. As a result, it can be decided whether a data group is transmitted and received correctly or not to test existence of inter-signal electromagnetic induction noise of the flat cable and normalcy of the flat cable and the signal transmission and receiving circuit.

8. 发明专利

JPS5330236A MEMORY TEST METHOD 失效
公开(公告)号：JPS5330236A
公开(公告)日：1978-03-22
申请号：JP10523676
申请日：1976-09-02
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： KISHI SEISHICHI , OONISHI NOBORU , KAWANOBE TADASHI , OOTSU YOSHIKATSU , OOMA TOSHIO
IPC分类号： G06F11/22 , G01R31/00 , G01R31/28 , G06F11/00 , G11C29/00 , G11C29/10
摘要： PURPOSE:To detect the fault of the MEQ address selection mechanism without being controlled by the physical structure of a large-capacity memory medium MEQ, and to secure a proportion between the access number to NEQ required until the test becomes possible.

10. 发明专利

JPS63267035A SIGNAL PROCESSOR 失效
公开(公告)号：JPS63267035A
公开(公告)日：1988-11-04
申请号：JP10007487
申请日：1987-04-24
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KISHI SEISHICHI
IPC分类号： H04K1/04
摘要： PURPOSE:To reduce the distortion of respective inverters by setting the sampling clocks of respective inverters to the integer-multiplied upper limit frequency of an input signal. CONSTITUTION:A band-pass filter LPF which extracts a first band-component from an input terminal INPUT input signal, a band-pass filter HPF which extracts only a second band-pass component from the input signal and an adder which adds respective components of switches SW1-SW23 output terminal OUTPUT. With setting the sampling clocks of the inverters INV1-INV7 to integer M-multiplied Nyquist rate and adding operation to only the code of a sampling value, the input signal is constituted so that it can be frequency- inverted. With changing the sampling clocks with the structure of respective inverters consisting a privacy telephone set preserved as it is, an optional band- pass width, division/inversion and frequency shift are executed, whereby a signal processor can economically be realized. Furthermore, the sampling clocks can be set to the integer-multiplied Nyquist rate, whereby attenuation distortion due to a 0 th sample hold effect (aperture effect) can be improved.

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