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1. 发明专利

DE4396525T1 未知
公开(公告)号：DE4396525T1
公开(公告)日：1997-04-17
申请号：DE4396525
申请日：1993-12-09
申请人： NIPPON DENSO CO
发明人： FUJIKAWA HISAYOSHI , OHWAKI TAKESHI , TAGA YASUNORI , TAKENAKA OSAMU , KONDO KENJI , YONEYAMA TAKAO , KONDO ICHIHARU
IPC分类号： H01L21/60 , H01L23/482 , H01L23/492 , H01L23/495 , H01L23/488 , H01R43/02

2. 发明专利

JPH0563188A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0563188A
公开(公告)日：1993-03-12
申请号：JP27143091
申请日：1991-10-18
申请人： NIPPON DENSO CO
发明人： KOMURA ATSUSHI , KONDO KENJI , KUROYANAGI AKIRA
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L29/78
摘要： PURPOSE:To provide a method for manufacturing a semiconductor device which can increase the spread of a sidewall made of an insulating film formed on the sidewall of a gate electrode by a novel method. CONSTITUTION:A polysilicon gate electrode material 11a is formed on a predetermined region on an N type epitaxial layer 2 through a gate oxide film 10. A CVD silicon oxide film 15 having a predetermined thickness is formed on the layer 2 including the material 11a, the film 15 is etched while supplying CHF3 gas in which hydrogen and fluorine are bonded to carbon and N2 gas by using a magnetron reactive ion etching unit to form a sidewall 16 only on the sidewall of the material 11a except the film 15. And, in the case where it is etched by using the etching unit, when CHF3/He/N2/O2 are used, contamination of the electrode is reduced.

3. 发明专利

JPS6484639A AL WIRING AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6484639A
公开(公告)日：1989-03-29
申请号：JP24235487
申请日：1987-09-25
申请人： NIPPON DENSO CO
发明人： KONDO KENJI , AKAMATSU KAZUO , YAMAUCHI TAKESHI , YAMAOKA TORU , KOMURA ATSUSHI
IPC分类号： H01L23/52 , H01L21/3205
摘要： PURPOSE:To inhibit the generation of an electromigration and to make long the longevity of an Al wiring by a method wherein nitrogen is contained in the Al wiring and the amount of this nitrogen is adjusted. CONSTITUTION:Ar gas, which is inert gas, is added in a chamber 5, which is brought in a vacuum state by a vacuum pump 6, being controlled by a mass flow controller 7 in such a way that its flow rate comes to 20cc/min. With that, N2 gas is added while its flow rate is controlled by a mass flow controller 7 in such a way as to come to 0.14-18cc/min. A high voltage is applied between a wafer holder 1 and a target 3 in a state that the amount of gas in the chamber 5 is adjusted and a reactive sputtering is performed to deposit an Al-Si-N2 thin film on the surface of a semiconductor wafer 2. This thin film is patterned by performing a photolithography process after that to form an Al wiring.

4. 发明专利

JPH06188359A LEAD FRAME 失效
公开(公告)号：JPH06188359A
公开(公告)日：1994-07-08
申请号：JP33593492
申请日：1992-12-16
申请人： NIPPON DENSO CO
发明人： KONDO KENJI
IPC分类号： H01L21/60 , H01L23/48 , H01L23/50
摘要： PURPOSE:To obtain a lead frame wherein, in a wire bonding process, the portions of a lead part and a support bar part which portions are pressed by a fixture become the same plane. CONSTITUTION:In a lead frame 1 turning to the terminal part of a resin-sealed semiconductor, the space between a wire bonding region 131 of a lead part 13 and an island part 11 is not different from the conventional one. In the connection part of a support bar part 12 and the island part 11, a rectangular notched parts 14 are formed in a part of the island part 11 of the side part of the support bar part 12. A depressed position 121 of the support bar part 12 is displaced from the wire bonding region of the lead part to the island part 11 side. Hence the lead frame can be fixed only by one fixture jig in a wire bonding process.

5. 发明专利

JPH0338039A DEVICE HAVING METAL WIRING LAYER AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0338039A
公开(公告)日：1991-02-19
申请号：JP17330389
申请日：1989-07-05
申请人： NIPPON DENSO CO
发明人： AKAMATSU KAZUO , KONDO KENJI , YAMAOKA TORU , YAMAUCHI TAKESHI , KOMURA ATSUSHI
IPC分类号： H01L23/522 , H01L21/318 , H01L21/768
摘要： PURPOSE:To reduce void, prevent imperfect wiring caused by stress migration, and extend the service life of wiring, by providing a passivation film or an interlayer insulating film with a lower part insulating film made of aluminum nitride and an upper part insulating film made of an insulator except aluminum nitride. CONSTITUTION:A passivation film or an interlayer insulating film of two-layer structure is provided. Said structure is constituted of a lower part insulating film 4 made of aluminum nitride and an upper part insulating film 5 made of insulator except aluminum nitride. Hence, at the time of forming the upper insulating 5, an aluminum wiring layer 3 is covered with the lower part insulating film 4 made of the Ai.N film which is hard and excellent in adhesion to the aluminum wiring layer 3. As a result, when the temperature of the aluminum wiring layer 3 rises high at the time of forming the upper part insulating film 5, thermal expansion and contraction of the aluminum wiring layer 3 can be restrained by the lower part insulating film 4, and therefore thermal stress caused by the difference between the thermal expansion coefficient of the upper part insulating film 5 and that of the aluminum wiring layer 3 is reduced. Thus void is reduced, imperfect wiring caused by stress migration is prevented, and the service life of wiring can be extended.

6. 发明专利

JPH02294061A MULTI CHIP PACKAGE STRUCTURE 失效
公开(公告)号：JPH02294061A
公开(公告)日：1990-12-05
申请号：JP11455989
申请日：1989-05-08
申请人： NIPPON DENSO CO
发明人： TSUZUKI YUKIO , KONDO KENJI
IPC分类号： H01L25/18 , H01L23/52 , H01L25/04
摘要： PURPOSE:To simplify manufacturing process and reduce cost, by bonding and fixing a relaying lead frame constituted of a part of lead frames and the lead frame by using a reinforcing resin film, and connecting chips by using the relaying lead frame. CONSTITUTION:A plurality of chips 11, 12 are directly mounted on a lead frame 13, and a relaying lead frame 16 formed by a frame constituting the lead frame 13 is arranged. The chips 11 and 12 are relayed and connected by said lead frame 16. The lead frame 13 and the relaying lead frame 16 are bonded and fixed by using a reinforcing film 17 composed of resin. As a result, the chip 11 and the chip 12 can be connected without especially arranging a relaying substrate and the like. Thereby the structure is simplified, and a multi chip package structure of low coat can be obtained.

7. 发明专利

JPS63253631A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS63253631A
公开(公告)日：1988-10-20
申请号：JP8818387
申请日：1987-04-10
申请人： NIPPON DENSO CO
发明人： YAMAUCHI TAKESHI , KONDO KENJI , KOMURA ATSUSHI , AKAMATSU KAZUO , HIGUCHI YASUSHI
IPC分类号： H01L21/302 , H01L21/3065
摘要： PURPOSE:To enable the formation of an opening such as viahole having a proper slope angle established in a uniform state by performing a reactive ion etching in a magnetron discharge atmosphere, and specifying the ratios between the deposition rate of the polymer generated by the discharge, the etch rate of the polymer and the etch rate of the insulating layer. CONSTITUTION:When a reactive ion etching using a magnetron device is performed to an opening 16 section formed vertically of an interlayer insulating layer 14, a plasma is generated, unsaturated carbon fluoride such as CF2 can easily be produced in the plasma, and a polymer having a composition of CxFy is effectively generated. Therefore, in that etching process, a polymer 30 deposits and adheres to the surface of a viahole 17, and the amount thereof is determined by the balance of the contentional etching-deposition reaction, whereby the etching shape can be controlled. And this etching reaction is governed by the ratio r between the deposition rate V1 of the polymer 30 and the etch rate V2 of this polymer and the ratio R between V2 and the etch rate V3 of the interlayer insulating layer 14, and the viahole having a tapered surface is formed with R>1 and r

8. 发明专利

JP2531173B2 失效
公开(公告)号：JP2531173B2
公开(公告)日：1996-09-04
申请号：JP8818387
申请日：1987-04-10
申请人： NIPPON DENSO CO
发明人： YAMAUCHI TAKESHI , KONDO KENJI , KOMURA ATSUSHI , AKAMATSU KAZUO , HIGUCHI YASUSHI
IPC分类号： H01L21/302 , H01L21/3065

9. 发明专利

JPH06163481A DRY ETCHING METHOD OF SEMICONDUCTOR 失效
公开(公告)号：JPH06163481A
公开(公告)日：1994-06-10
申请号：JP33363892
申请日：1992-11-18
申请人： NIPPON DENSO CO
发明人： KOMURA ATSUSHI , SAKANO YOSHIKAZU , KONDO KENJI , MIURA SHOJI , KIN HIROITSU , SANPEI TETSUHIKO
IPC分类号： H01L21/302 , H01L21/3065
摘要： PURPOSE:To enable a preferable deep trench in good shape and reproducibility to be efficiently formed with high precision by a method wherein the mixed gas comprising a bromine containing gas, a halogen element containing gas and nitrogen gas is used as an etching gas of a silicon substrate. CONSTITUTION:A silicon substrate 308 is dry etched away using the mixed gas comprising a bromine containing gas, a halogen element containing gas and nitrogen gas. At this time, the flow rate of nitrogen gas is specified to have a specific ratio to that of the bromine containing gas for controlling the etching rate and the inclination of the deep trench. For example, an RIE device as shown in figure is used so that the Si substrate 308 may be arranged on a lower electrode 305 to lead-in an etching gas comprising HBr, SF6 and N2 from a gas leading-in port 302 for exhausting the etching gas from an exhaust port 303. Finally, the space between electrodes 304, 305 is fed with a power of 13.56MHz from a high frequency power supply 306 to produce gas plasma in the same space between the electrodes 304, 305 for etching away the Si substrate 308.

10. 发明专利

JPH01128447A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01128447A
公开(公告)日：1989-05-22
申请号：JP28574587
申请日：1987-11-12
申请人： NIPPON DENSO CO
发明人： YAMAUCHI TAKESHI , KOMURA ATSUSHI , KONDO KENJI , AKAMATSU KAZUO , TAKENAKA OSAMU , HIGUCHI YASUSHI
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768
摘要： PURPOSE:To realize flattening without steps which cause constriction or cutting off when forming a metal wiring layer, by carrying out etchback by making plasma-etching on the entire surface of an interlayer insulation layer provided with a via hole. CONSTITUTION:After wiring layers 241, 242 of a primary layer are formed, an interlayer insulation layer 25 is formed on the entire surface of a semiconductor substrate 21 including the wiring layers 241, 242. Then a via hole 27 reaching the wiring layer 241 is formed by etching corresponding to the wiring layer 241 on the interlayer insulation layer 25 which has surface irregularities. The surface of the interlayer insulation layer 25 is entirely etched by reactive ion etching. By this etching process, tapered surface 281, 282,... which continue in the inclines, and a tapered surface 29 of inner circumference whose diameter is larger at the opening are shaped. A wiring layer 30 of a secondary layer is formed on the surface of the interlayer insulation layer 25 thus connecting a wiring layers 241 and 30 through the via hole 27 which has a tapered surface.

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