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1. 发明公开

KR20070081095A MULTIPROCESSOR SYSTEM AND BOOT-UP METHOD OF SLAVE SYSTEM 审中-公开
标题翻译：多处理器系统和从动系统的启动方法
公开(公告)号：KR20070081095A
公开(公告)日：2007-08-14
申请号：KR20070012747
申请日：2007-02-07
申请人： NEC ELECTRONICS CORP
发明人： UEMURA MARIKO , SUDA KEI
IPC分类号： G06F9/24
CPC分类号： G06F15/177 , G06F9/4405
摘要： A multiprocessor system and a method for booting a slave system are provided to reduce the number of components by not requiring the slave system having a program memory for storing a booting program and to simplify configuration of a loader by downloading the booting program through an inter-processor communication interface. The multiprocessor system includes the master system(10) and the slave system(20) connected to the master system through the inter-processor communication interface. The master system includes a program ROM(13) for storing the booting program for the slave system. The slave system includes the loader(25) for downloading the booting program from the program ROM of the master through the inter-processor communication interface. The loader includes a unit for transmitting confirming execution of a transmitted download command to a CPU(11) of the master system, and a storing unit for receiving and storing the booting program to a RAM(22).
摘要翻译：提供了一种用于引导从系统的多处理器系统和方法，用于通过不需要具有用于存储引导程序的程序存储器的从系统来简化组件的数量，并且通过下载引导程序来简化加载程序的配置。处理器通信接口。多处理器系统包括通过处理器间通信接口连接到主系统的主系统（10）和从系统（20）。主系统包括用于存储从系统的引导程序的程序ROM（13）。从系统包括用于通过处理器间通信接口从主机的程序ROM下载引导程序的加载程序（25）。该加载器包括用于向主系统的CPU（11）发送确认执行发送的下载命令的单元，以及用于接收并将引导程序存储到RAM（22）的存储单元。

2. 发明专利

GB2435118B Multiprocessor system and boot-up method of slave system 未知
公开(公告)号：GB2435118B
公开(公告)日：2008-01-09
申请号：GB0701441
申请日：2007-01-25
申请人： NEC ELECTRONICS CORP
发明人： UEMURA MARIKO , SUDA KEI
IPC分类号： G06F9/445
摘要： To provide a multiprocessor system and a boot-up method of a slave system, which can reduce the number of components with simple configuration. A multiprocessor system according to an embodiment of the present invention includes a master system, and a slave system connected with the master system through an interprocessor communication interface. The master system includes a program ROM storing a boot program for the slave system. The slave system includes a loader downloading the boot program stored in the program ROM through the interprocessor communication interface.

3. 发明专利

GB2435118A Method of booting up a slave processor by the boot loader of the slave loading the boot program from the memory attached to the master processor. 未知
公开(公告)号：GB2435118A
公开(公告)日：2007-08-15
申请号：GB0701441
申请日：2007-01-25
申请人： NEC ELECTRONICS CORP
发明人： UEMURA MARIKO , SUDA KEI
IPC分类号： G06F9/445
摘要： Disclosed is a multiprocessor system and a method of booting up the slave processor 21 of the system. The system consists of a master system 10 and a slave system 20, connected to each other by an inter-processor communication interface 14, 23. The master system has a memory 13 to store the boot program for the slave system. The slave system has a loader 25 to download its boot program from the memory attached to the master system via the inter-processor communication interface. The slave system may have a memory 22 to store the program to be executed by the slave processor. The master system may issue a command to the loader of the slave system to load the boot program and the loader issue a message confirming that the boot program is being downloaded. The inter-processor communication interface may be a serial interface. The slave system thus does not need it own non-volatile memory to store its boot-up or BIOS program.

4. 发明专利

GB2435118C Multiprocessor system and boot-up method of slave system. 未知
公开(公告)号：GB2435118C
公开(公告)日：2008-01-14
申请号：GB0701441
申请日：2007-01-25
申请人： NEC ELECTRONICS CORP
发明人： UEMURA MARIKO , SUDA KEI
IPC分类号： G06F9/445
摘要： To provide a multiprocessor system and a boot-up method of a slave system, which can reduce the number of components with simple configuration. A multiprocessor system according to an embodiment of the present invention includes a master system, and a slave system connected with the master system through an interprocessor communication interface. The master system includes a program ROM storing a boot program for the slave system. The slave system includes a loader downloading the boot program stored in the program ROM through the interprocessor communication interface.

5. 发明专利

GB2371721B Mobile phone capable of stopping main clock signal 未知
公开(公告)号：GB2371721B
公开(公告)日：2003-07-23
申请号：GB0128642
申请日：2001-11-29
申请人： NEC CORP , NEC ELECTRONICS CORP
发明人： SUDA KEI
IPC分类号： H04B1/16 , H04B1/3822 , H04B1/40 , H04B7/26 , H04M1/725 , H04M1/73 , H04W52/02 , H04W88/02 , H04Q7/32
摘要： A mobile phone has at least one main clock system and operating based on a main clock signal of the main clock system. The main clock system includes a main counter for counting main clocks of the main clock signal; and a power saving section for stopping generation of the main clock signal for a time period, while counting wait clocks of a wait clock signal, for restarting the generation of the main clock signal after the time period, and for controlling the main counter the main counter based on the counted wait clocks as if the main counter always counts the main clocks of the main clock signal.

6. 发明专利

GB2344259B Device and method for perch channel reception for mobile radio communication terminal 未知
公开(公告)号：GB2344259B
公开(公告)日：2003-04-16
申请号：GB9923295
申请日：1999-10-01
申请人： NEC CORP , NEC ELECTRONICS CORP
发明人： SUDA KEI
IPC分类号： H04B1/707 , H04B1/7083 , H04B7/26 , H04L7/00 , H04W56/00 , H04W76/02
摘要： A perch channel reception device of a mobile radio communication terminal for successively receiving perch channels of base stations around the terminal includes a delay profile generator, a base station scrambling timing detector, a timing corrector, a correlator with time window, and a perch channel demodulator. The delay profile generator detects frame boundary symbols included in a received modulated radio wave and thereby generates a delay profile. The base station scrambling timing detector detects scrambling timing of each base station based on the delay profile. Thereafter, a base station is selected from the base stations one by one as the object of perch channel reception. The timing corrector calculates corrected scrambling timing of the selected base station using a timing correction supplied from the correlator with time window and the scrambling timing of the selected base station based on the delay profile. The correlator with time window takes the correlation between the received modulated radio wave and the scrambling code of the selected base station, with respect to a plurality of comparison starting times in a time window around the corrected scrambling timing, and thereby generates correlation data and the timing correction. The perch channel demodulator demodulates the correlation data into logic data including information concerning the selected base station.

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