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1. 发明申请

WO2012046864A2 MULTICORE TYPE ERROR CORRECTION PROCESSING SYSTEM AND ERROR CORRECTION PROCESSING APPARATUS 审中-公开
标题翻译：多种类型错误校正处理系统和错误校正处理设备
公开(公告)号：WO2012046864A2
公开(公告)日：2012-04-12
申请号：PCT/JP2011/073281
申请日：2011-10-04
申请人： NEC Corporation , Technische Universität Dresden , KOBORI, Tomoyoshi , KUNZE, Steffen , MATUS, Emil , FETTWEIS, Gerhard
发明人： KOBORI, Tomoyoshi , KUNZE, Steffen , MATUS, Emil , FETTWEIS, Gerhard
CPC分类号： G06F11/1044 , G06F5/015 , H03M13/1102 , H03M13/1105 , H03M13/114 , H03M13/1145 , H03M13/1162 , H03M13/1171 , H03M13/2775 , H03M13/296 , H03M13/2978 , H03M13/6508 , H03M13/6513 , H03M13/6566 , H03M13/6569 , H03M13/6577
摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.
摘要翻译：在能够同时处理多个纠错方法和多个码长的多核型纠错处理系统中，互连部分11具有延伸跨越多个纠错处理部分12a-12c的桶形移位器。可以通过集体地使用多个纠错处理部分12a-12c的组或者通过单独地使用每个单独的纠错处理部分12a-12c来响应于互连配置信息来选择性地执行纠错处理。利用这种结构，如果计算资源不足，则多个纠错处理部分12a-12c被共同使用，并且如果计算资源过多，则将空闲纠错处理部分分配给另一纠错处理部分。

2. 发明申请

WO2012111846A1 TURBO DECODER WITH QPP OR ARP INTERLEAVER 审中-公开
标题翻译： TURBO解码器与QPP或ARP交互
公开(公告)号：WO2012111846A1
公开(公告)日：2012-08-23
申请号：PCT/JP2012/054179
申请日：2012-02-15
申请人： NEC Corporation , Technische Universitaet Dresden , KOBORI, Tomoyoshi , KUNZE, Steffen , MATUS, Emil , FETTWEIS, Gerhard
发明人： KOBORI, Tomoyoshi , KUNZE, Steffen , MATUS, Emil , FETTWEIS, Gerhard
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2753 , H03M13/2739 , H03M13/2764 , H03M13/2957 , H03M13/3972 , H03M13/6525 , H03M13/6544
摘要： An interleave address generating circuit of a multicore type turbo decode processing apparatus of the present invention includes intermediate value generating blocks whose arithmetic portions are modified so as to generate not only an interleave address corresponding to the forward direction but also an interleave address corresponding to the backward direction. By using initial parameters which are preliminarily decomposed into parameters for a memory bank and physical addresses, the intermediate value generating blocks having a restricted bit width in two parallel are disposed in two parallel and the two intermediate value generating blocks are connected to each other through signal lines for exchanging carry signals.
摘要翻译：本发明的多核型turbo解码处理装置的交织地址生成电路包括中间值生成块，其运算部分被修改为不仅产生与前向相对应的交织地址，而且还生成与后向对应的交织地址方向。通过使用预先分解为存储体和物理地址的参数的初始参数，具有两个并联的受限位宽的中间值生成块被布置成并联，并且两个中间值生成块通过信号彼此连接用于交换进位信号的线路。

3. 发明公开

EP2625787A2 MULTICORE TYPE ERROR CORRECTION PROCESSING SYSTEM AND ERROR CORRECTION PROCESSING APPARATUS 审中-公开
标题翻译：系统和设备多核处理纠错
公开(公告)号：EP2625787A2
公开(公告)日：2013-08-14
申请号：EP11773571.2
申请日：2011-10-04
申请人： NEC Corporation , Technische Universität Dresden
发明人： KOBORI, Tomoyoshi , KUNZE, Steffen , MATUS, Emil , FETTWEIS, Gerhard
IPC分类号： H03M13/11 , H03M13/29
CPC分类号： G06F11/1044 , G06F5/015 , H03M13/1102 , H03M13/1105 , H03M13/114 , H03M13/1145 , H03M13/1162 , H03M13/1171 , H03M13/2775 , H03M13/296 , H03M13/2978 , H03M13/6508 , H03M13/6513 , H03M13/6566 , H03M13/6569 , H03M13/6577
摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

4. 发明公开

EP2676373A1 TURBO DECODER WITH QPP OR ARP INTERLEAVER 审中-公开
标题翻译：以有或QPP ARP交织Turbo译码
公开(公告)号：EP2676373A1
公开(公告)日：2013-12-25
申请号：EP12707938.2
申请日：2012-02-15
申请人： NEC Corporation , Technische Universität Dresden
发明人： KOBORI, Tomoyoshi , KUNZE, Steffen , MATUS, Emil , FETTWEIS, Gerhard
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2753 , H03M13/2739 , H03M13/2764 , H03M13/2957 , H03M13/3972 , H03M13/6525 , H03M13/6544
摘要： An interleave address generating circuit of a multicore type turbo decode processing apparatus of the present invention includes intermediate value generating blocks whose arithmetic portions are modified so as to generate not only an interleave address corresponding to the forward direction but also an interleave address corresponding to the backward direction. By using initial parameters which are preliminarily decomposed into parameters for a memory bank and physical addresses, the intermediate value generating blocks having a restricted bit width in two parallel are disposed in two parallel and the two intermediate value generating blocks are connected to each other through signal lines for exchanging carry signals.

5. 发明申请

WO2004052723A1 LUFTFAHRZEUG-TÜRANORDNUNG 审中-公开
标题翻译：飞机舱门安排
公开(公告)号：WO2004052723A1
公开(公告)日：2004-06-24
申请号：PCT/EP2003/013752
申请日：2003-12-05
申请人： EUROCOPTER DEUTSCHLAND GMBH , WIERS, Andreas , SUCHY, Rainer , KUNZE, Steffen , STERR, Matthias
发明人： WIERS, Andreas , SUCHY, Rainer , KUNZE, Steffen , STERR, Matthias
IPC分类号： B64C1/14
CPC分类号： B64C1/143 , B64C1/1407
摘要： Luftfahrzeug-Türanordnung, insbesondere für ein Flugzeug, umfassend eine Tür; einen Türrahmen; einen Traglenker mit einer türseitigen Schwenkachse (AD), an der die Tür schwenkbar gelagert ist, und einer rahmenseitigen Schwenkachse (AF), an welcher der Traglenker (8) schwenkbar am Türrahmen gelagert ist, wobei zumindest die türseitige Schwenkachse (AD) durch zwei in Höhenrichtung (Y) des Traglenkers (8) voneinander beabstandete Gelenke (G1, G2) definiert ist, von denen mindestens eines (G1; G2) zwei in Höhenrichtung (Y) voneinander beabstandete Lagerstellen (L1a, L1b) besitzt; einen am türseitigen Bereich des Traglenkers (8) angeordneten Schwenkantrieb (10) zum Verschwenken der Tür; und ein Abtriebselement (12; 14, 16), welches mit dem Schwenkantrieb (10) und der Tür gekoppelt ist und eine Stellbewegung des Schwenkantriebs (10) auf die Tür überträgt. Die Luftfahrzeug-Türanordnung ist dadurch gekennzeichnet, dass eine (L1b) der zwei Lagerstellen (L1a, L1b) von mindestens einem (G1) der rahmenseitigen Gelenke (G1, G2) als ein Schwenkantrieb-Lagerbeschlag (34) ausgebildet ist (L1B), an dem der Schwenkantrieb (10) befestigt ist.
摘要翻译：飞机门装置，特别是用于飞行器，包括门; 门框; 支撑连杆具有门侧回转轴线（AD），在该门枢转地安装，并且框架侧旋转轴（AF），在该支承臂（8）枢转地安装在门框上，其中，至少所述门侧回转轴线（AD）由两个高度方向上彼此支撑臂（8）间隔开的接头（G1，G2）的（Y）被定义，其中至少一个（G1; G2）的间隔开的支承点（L1A，L1b）表示具有有两个在垂直方向（Y）; 用于转动所述门设置在所述支撑臂的门侧部分（8）枢转驱动器（10）; 和输出构件（12; 14，16）连接到所述枢转驱动器（10）和所述门耦接，并且旋转致动器（10）的致动运动传递到门。飞机门装置的特征在于：一个框架侧接头的两个支承点的（L1b）表示（L1A，L1b）表示的至少一种（G1）（G1，G2）被设计为旋转致动器轴承嵌合（34）（L1B），以该枢转驱动器（10）附连。

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