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1. 发明专利

DE60007218T2 未知
公开(公告)号：DE60007218T2
公开(公告)日：2004-09-02
申请号：DE60007218
申请日：2000-04-28
申请人： NEC CORP
发明人： UEMURA TETSUYA
IPC分类号： H03K3/313 , G11C5/14 , H03K3/315 , H03K3/289 , H01L27/092 , H01L21/8238 , H03K3/13
摘要： The flip-flop circuit includes: a series (8) circuit which has a negative differential resistance element (1) and another negative differential resistance element (2) that has a control terminal capable of controlling a value of an element current; a transfer gate (9); a latch circuit (10) which has negative differential resistance elements (4), (5) connected in series; and an inverter circuit (11) which has an FET (6) as a drive element and a negative differential resistance element (7) as a load element. With this, such a flip-flop can be obtained that when a clock signal (CLK) is applied to a power supply terminal DD1 of the series circuit (8) and a control terminal of the transfer gate (9) and an input signal (IN) is supplied to the control terminal of the negative differential resistance element (2), an output is placed at a terminal.

2. 发明专利

DE10125368A1 未知
公开(公告)号：DE10125368A1
公开(公告)日：2002-02-07
申请号：DE10125368
申请日：2001-05-23
申请人： NEC CORP
发明人： UEMURA TETSUYA
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/10 , H01L29/205 , H01L29/732 , H01L29/737 , H01L31/0328
摘要： A differential negative resistance element includes a heavily doped GaAs layer interposed between a collector layer of lightly doped GaAs and an emitter layer of heavily doped AlGaAs, is shared between a base region between the collector layer and the emitter layer, a base contact region and a channel region between the base region and the base contact region, and a depletion layer is developed into the channel region together with the collector voltage so as to exhibit a differential negative resistance characteristics, wherein the channel region is formed through an epitaxial growth and etching so that the manufacturer easily imparts target differential negative resistance characteristics to the channel region.

3. 发明专利

DE69202554D1 未知
公开(公告)号：DE69202554D1
公开(公告)日：1995-06-22
申请号：DE69202554
申请日：1992-12-24
申请人： NEC CORP
发明人： BABA TOSHIO , UEMURA TETSUYA
IPC分类号： H01L29/739 , H01L29/72
摘要： The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction type to that of the first semiconductor are connected on a substrate or a laminated layer structure comprising a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor of the reverse conduction type to that of the first semiconductor all laminated on a part of a substrate. The tunnel transistor further includes a fourth semiconductor layer formed on an exposed surface of the second semiconductor, having a forbidden band wider than that of the second semiconductor and containing an ionized impurity therein, a gate electrode formed on the fourth semiconductor layer, and a pair of electrodes individually forming ohmic junctions to the first and third semiconductors. Due to the construction, even when the gate voltage is 0, electrons or positive holes are induced in the surface of the second semiconductor, and a tunnel current can be flowed between the source and the drain. Since control of the tunnel current can then be performed by applying a reverse bias voltage between the gate and the drain, the leak current of the gate can be suppressed.

4. 发明专利

DE69202554T2 未知
公开(公告)号：DE69202554T2
公开(公告)日：1995-10-19
申请号：DE69202554
申请日：1992-12-24
申请人： NEC CORP
发明人： BABA TOSHIO , UEMURA TETSUYA
IPC分类号： H01L29/739 , H01L29/72
摘要： The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction type to that of the first semiconductor are connected on a substrate or a laminated layer structure comprising a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor of the reverse conduction type to that of the first semiconductor all laminated on a part of a substrate. The tunnel transistor further includes a fourth semiconductor layer formed on an exposed surface of the second semiconductor, having a forbidden band wider than that of the second semiconductor and containing an ionized impurity therein, a gate electrode formed on the fourth semiconductor layer, and a pair of electrodes individually forming ohmic junctions to the first and third semiconductors. Due to the construction, even when the gate voltage is 0, electrons or positive holes are induced in the surface of the second semiconductor, and a tunnel current can be flowed between the source and the drain. Since control of the tunnel current can then be performed by applying a reverse bias voltage between the gate and the drain, the leak current of the gate can be suppressed.

5. 发明专利

DE60007218D1 未知
公开(公告)号：DE60007218D1
公开(公告)日：2004-01-29
申请号：DE60007218
申请日：2000-04-28
申请人： NEC CORP
发明人： UEMURA TETSUYA
IPC分类号： H03K3/313 , G11C5/14 , H03K3/315 , H03K3/289 , H01L27/092 , H01L21/8238 , H03K3/13
摘要： The flip-flop circuit includes: a series (8) circuit which has a negative differential resistance element (1) and another negative differential resistance element (2) that has a control terminal capable of controlling a value of an element current; a transfer gate (9); a latch circuit (10) which has negative differential resistance elements (4), (5) connected in series; and an inverter circuit (11) which has an FET (6) as a drive element and a negative differential resistance element (7) as a load element. With this, such a flip-flop can be obtained that when a clock signal (CLK) is applied to a power supply terminal DD1 of the series circuit (8) and a control terminal of the transfer gate (9) and an input signal (IN) is supplied to the control terminal of the negative differential resistance element (2), an output is placed at a terminal.

6. 发明专利

HK1054275A1 A memory device 未知
公开(公告)号：HK1054275A1
公开(公告)日：2003-11-21
申请号：HK03106437
申请日：2003-09-10
申请人： NEC CORP
发明人： UEMURA TETSUYA
IPC分类号： G11C20060101 , G11C11/38 , G11C11/36 , H01L27/10
摘要： A memory cell is formed by an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a first power supply; a first negative differential resistance element provided between the word line and the source of the FET; and a second negative differential resistance element provided between the source of the FET and a second power supply.

7. 发明专利

DE60233624D1 未知
公开(公告)号：DE60233624D1
公开(公告)日：2009-10-22
申请号：DE60233624
申请日：2002-07-18
申请人： NEC CORP
发明人： UEMURA TETSUYA
IPC分类号： G11C11/38 , G11C11/401 , G11C11/36 , H01L27/10
摘要： A memory cell is formed by an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a first power supply; a first negative differential resistance element provided between the word line and the source of the FET; and a second negative differential resistance element provided between the source of the FET and a second power supply.

8. 发明专利

DE69218893T2 未知
公开(公告)号：DE69218893T2
公开(公告)日：1997-09-04
申请号：DE69218893
申请日：1992-12-02
申请人： NEC CORP
发明人： UEMURA TETSUYA
IPC分类号： H01L29/73 , H01L21/331 , H01L29/66 , H01L29/737 , H01L29/739
摘要： A tunneling transistor comprising an emitter layer, a barrier layer having a conduction band higher in energy than a conduction band of said emitter layer and a valence band lower in energy than a valence band of said emitter layer, and further having a thickness with which electrons can substantially tunnel the barrier layer, a collector layer having a conduction band lower in energy than the valence band of said emitter layer and a conductivity type opposite to said emitter layer, and further having a thickness with which quantum levels are substantially formed, a gate layer having a conduction band higher in energy than the conduction band of said layer and a valence band of said emitter layer, and further having a thickness with which the probability of electron tunneling is substantially greatly reduced, said layers been laminated in this order, and electrodes which form ohmic junctions on said emitter layer and said collector layer and an electrode which forms a Schottky junction on said gate layer.

9. 发明专利

DE69218893D1 未知
公开(公告)号：DE69218893D1
公开(公告)日：1997-05-15
申请号：DE69218893
申请日：1992-12-02
申请人： NEC CORP
发明人： UEMURA TETSUYA
IPC分类号： H01L29/73 , H01L21/331 , H01L29/66 , H01L29/737 , H01L29/739
摘要： A tunneling transistor comprising an emitter layer, a barrier layer having a conduction band higher in energy than a conduction band of said emitter layer and a valence band lower in energy than a valence band of said emitter layer, and further having a thickness with which electrons can substantially tunnel the barrier layer, a collector layer having a conduction band lower in energy than the valence band of said emitter layer and a conductivity type opposite to said emitter layer, and further having a thickness with which quantum levels are substantially formed, a gate layer having a conduction band higher in energy than the conduction band of said layer and a valence band of said emitter layer, and further having a thickness with which the probability of electron tunneling is substantially greatly reduced, said layers been laminated in this order, and electrodes which form ohmic junctions on said emitter layer and said collector layer and an electrode which forms a Schottky junction on said gate layer.

10. 发明专利

JPH07231085A TUNNEL TRANSISTOR AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH07231085A
公开(公告)日：1995-08-29
申请号：JP2072294
申请日：1994-02-18
申请人： NEC CORP
发明人： BABA TOSHIO , UEMURA TETSUYA
IPC分类号： H01L29/68 , H01L29/06 , H01L29/78 , H01L29/86
摘要： PURPOSE:To provide a transistor utilizing tunnel phenomenon which can be highly integrated, speeded up, and multi-functional. CONSTITUTION:The item is provided with a first semiconductor 2 of one conductivity type, a separation layer 3 consisting of a low-impurity concentration semiconductor, and a degenerated second semiconductor 4 with a conductivity type opposite to that of the first semiconductor 2 on a substrate 1. Therefore, a degenerated third semiconductor 5 with the same conductivity type as that of the first semiconductor 2, an insulation layer 6 consisting of a material with a wider forbidden band than that of the third semiconductor 5, and a gate electrode 7 on the insulation layer 6 are provided on the exposed surface of the second semiconductor 4 from the first semiconductor 2 and a ohmic junction is formed on the first semiconductor 2 and the second semiconductor 4 in a drain electrode 8 and a source electrode 9.

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