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1. 发明公开

EP0851356A2 Multiprocessor computer system 失效
标题翻译： Multiprozessor-Rechnersystem
公开(公告)号：EP0851356A2
公开(公告)日：1998-07-01
申请号：EP97308077.3
申请日：1997-10-13
申请人： NCR INTERNATIONAL INC.
发明人： Young, Gene F. , James, Larry C. , Stevens, Roy M.
IPC分类号： G06F12/08
CPC分类号： G06F12/0826 , G06F12/0813 , G06F12/082
摘要： The present invention relates to a multiprocessor computer system having comprising a plurality of processors and a memory system including a system memory shared by the plurality of processors together with data cache memories, at least one data cache memory associated with each one of said processors.
The computer system employs a directory based cache coherency scheme for maintaining consistency between lines of data residing in the shared system memory and lines of data residing in the data cache memories. The coherency scheme depends on storing line status information for lines of the shared system memory. The provision for storing line status information comprises a state cache memory associated with the shared system memory to cache the memory line status information. The state cache memory is sized to store status information for a portion only of the memory lines in the shared system memory (e.g. one sixteenth of the memory lines in the shared system memory) and can be a direct mapped cache.
摘要翻译：多处理器计算机系统本发明涉及一种具有多个处理器的多处理器计算机系统和包括由数据高速缓存存储器与多个处理器共享的系统存储器的存储器系统，至少一个与所述处理器中的每一个相关联的数据高速缓冲存储器。计算机系统采用基于目录的高速缓存一致性方案来维持驻留在共享系统存储器中的数据线与驻留在数据高速缓冲存储器中的数据线之间的一致性。一致性方案取决于存储共享系统内存线路的线路状态信息。用于存储线路状态信息的提供包括与共享系统存储器相关联的状态高速缓冲存储器，以缓存存储器线路状态信息。状态高速缓冲存储器的大小设置为仅存储共享系统存储器（例如，共享系统存储器中的存储器线路的十六分之一）中的存储器线路的一部分的状态信息，并且可以是直接映射高速缓存。

2. 发明公开

EP0847011A2 Method for reducing the number of coherency cycles within a directory-based cache coherency memory system utilizing a memory state cache 失效
标题翻译：一种用于使用存储器状态高速缓存存储器在减少基于目录的高速缓存一致性存储器体系相干性周期的数量的方法
公开(公告)号：EP0847011A2
公开(公告)日：1998-06-10
申请号：EP97308075.7
申请日：1997-10-13
申请人： NCR INTERNATIONAL INC.
发明人： Young, Gene F. , James, Larry C. , Stevens, Roy M.
IPC分类号： G06F12/08
CPC分类号： G06F12/082
摘要： The present invention relates to a method for replacing entries within a state cache memory of a multiprocessor computer system. The computer system has, in addition to the state cache memory, a shared system memory, a plurality of data cache memories, a system of busses interconnecting the system memory with the data cache memories, and employs a centralised/distributed directory based cache coherency scheme for maintaining consistency between lines of memory within said shared system memory and the data cache memories.
The method establishes a default memory state of SHARED for lines of memory represented in the state cache memory. The system memory line state for a state cache entry associated with a line of memory stored in the shared memory and at least one data cache memory is read prior to its replacement. A castout operation updates the line of memory within the shared memory and assigns a data cache memory line state of SHARED to the line of memory in each data cache memory if the system memory line state is OWNED.
摘要翻译：本发明涉及一种用于在多处理器计算机系统的一个状态高速缓存存储器中替换项的方法，该计算机系统具有，除了状态高速缓存存储器，共享系统存储器，数据高速缓冲存储器复数，总线的系统互连与所述数据高速缓冲存储器的系统存储器，和采用了集中式和/或分布的基于目录的高速缓存一致性保持所述共享系统存储器内的存储器线和数据高速缓冲存储器之间的一致性方案。该方法建立SHARED的在状态高速缓存存储器为代表的存储器线默认的存储器状态。用于与存储在所述共享存储器和至少一个数据高速缓冲存储器的线的存储器相关联的状态高速缓存条目中的系统存储器线状态之前其更换被读取。甲castout操作更新的共享存储器内的存储器行，并分配在系统存储器线状态被拥有的共享到的存储器中的每个数据高速缓冲存储器的线的数据高速缓冲存储器线的状态。

3. 发明公开

EP0847011A3 Method for reducing the number of coherency cycles within a directory-based cache coherency memory system utilizing a memory state cache 失效
标题翻译：一种用于使用存储器状态高速缓存存储器在减少基于目录的高速缓存一致性存储器体系相干性周期的数量的方法
公开(公告)号：EP0847011A3
公开(公告)日：1999-12-29
申请号：EP97308075.7
申请日：1997-10-13
申请人： NCR INTERNATIONAL INC.
发明人： Young, Gene F. , James, Larry C. , Stevens, Roy M.
IPC分类号： G06F12/08
CPC分类号： G06F12/082
摘要： The present invention relates to a method for replacing entries within a state cache memory of a multiprocessor computer system. The computer system has, in addition to the state cache memory, a shared system memory, a plurality of data cache memories, a system of busses interconnecting the system memory with the data cache memories, and employs a centralised/distributed directory based cache coherency scheme for maintaining consistency between lines of memory within said shared system memory and the data cache memories. The method establishes a default memory state of SHARED for lines of memory represented in the state cache memory. The system memory line state for a state cache entry associated with a line of memory stored in the shared memory and at least one data cache memory is read prior to its replacement. A castout operation updates the line of memory within the shared memory and assigns a data cache memory line state of SHARED to the line of memory in each data cache memory if the system memory line state is OWNED.

4. 发明公开

EP0851356A3 Multiprocessor computer system 失效
标题翻译：多处理器计算机系统
公开(公告)号：EP0851356A3
公开(公告)日：1999-12-22
申请号：EP97308077.3
申请日：1997-10-13
申请人： NCR INTERNATIONAL INC.
发明人： Young, Gene F. , James, Larry C. , Stevens, Roy M.
IPC分类号： G06F12/08
CPC分类号： G06F12/0826 , G06F12/0813 , G06F12/082
摘要： The present invention relates to a multiprocessor computer system having comprising a plurality of processors and a memory system including a system memory shared by the plurality of processors together with data cache memories, at least one data cache memory associated with each one of said processors.
The computer system employs a directory based cache coherency scheme for maintaining consistency between lines of data residing in the shared system memory and lines of data residing in the data cache memories. The coherency scheme depends on storing line status information for lines of the shared system memory. The provision for storing line status information comprises a state cache memory associated with the shared system memory to cache the memory line status information. The state cache memory is sized to store status information for a portion only of the memory lines in the shared system memory (e.g. one sixteenth of the memory lines in the shared system memory) and can be a direct mapped cache.

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