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    • 2. 发明授权
    • Distributed processing apparatus and method for processing large data through hardware acceleration
    • 通过硬件加速处理大数据的分布式处理设备和方法
    • US09342564B2
    • 2016-05-17
    • US13590805
    • 2012-08-21
    • Myung-June JungJu-Pyung Lee
    • Myung-June JungJu-Pyung Lee
    • G06F15/76G06F7/38G06F17/30
    • G06F17/30545
    • A distributed data processing apparatus and method through hardware acceleration are provided. The data processing apparatus includes a mapping node including mapping units configured to process input data in parallel to generate and output mapping results. The data processing apparatus further includes a shuffle node including shuffle units and a memory buffer, the shuffle units configured to process the mapping results output from the mapping units in parallel to generate and output shuffle results, and the shuffle node configured to write the shuffle results output from the shuffle units in the memory buffer. The data processing apparatus further includes a merge node including merge units configured to merge the shuffle results written in the memory buffer to generate merging results.
    • 提供了一种通过硬件加速的分布式数据处理装置和方法。 数据处理装置包括映射节点,其包括被配置为并行处理输入数据的映射单元,以生成和输出映射结果。 所述数据处理装置还包括包括随机单元和存储器缓冲器的混洗节点,所述混洗单元被配置为并行处理从所述映射单元输出的映射结果,以生成和输出随机播放结果,并且所述随机播放节点被配置为写入所述随机播放结果 从内存缓冲区中的随机播放单元输出。 数据处理装置还包括合并节点,其包括被配置为合并写入存储器缓冲器中的混洗结果以产生合并结果的合并单元。
    • 6. 发明授权
    • Interrupt on/off management apparatus and method for multi-core processor
    • 多核处理器的中断开/关管理装置和方法
    • US08892803B2
    • 2014-11-18
    • US12880335
    • 2010-09-13
    • Ju-Pyung Lee
    • Ju-Pyung Lee
    • G06F13/24
    • G06F13/24
    • Provided are an interrupt on/off management apparatus and method for a multi-core processor having a plurality of central processing unit (CPU) cores. The interrupt on/off management apparatus manages the multi-core processor such that at least one of two or more CPU cores included in a target CPU set can execute an urgent interrupt. For example, the interrupt on/off management apparatus controls the movement of each CPU core from a critical section to a non-critical section such that at least one of the CPU cores is located in the non-critical section. The critical section may include an interrupt-disabled section or a kernel non-preemptible section, and the non-critical section may include an interrupt-enabled section or include both of the interrupt-enabled section and a kernel preemptible section.
    • 提供一种用于具有多个中央处理单元(CPU)核心的多核处理器的中断开/关管理装置和方法。 中断开/关管理装置管理多核处理器,使得包括在目标CPU集中的两个或多个CPU核中的至少一个可执行紧急中断。 例如,中断开/关管理装置控制每个CPU核心从关键部分到非关键部分的移动,使得至少一个CPU核心位于非关键部分。 关键部分可以包括中断禁止部分或内核非可抢占部分,并且非关键部分可以包括启用中断的部分或者包括中断使能部分和内核可抢占部分。