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1. 发明授权

US08068077B2 Contact structure of conductive films and thin film transistor array panel including the same 有权
标题翻译：导电膜和薄膜晶体管阵列面板的接触结构包括它们
公开(公告)号：US08068077B2
公开(公告)日：2011-11-29
申请号：US12407626
申请日：2009-03-19
申请人： Myung-Jae Park , Hyang-Shik Kong , Myung-Koo Hur , Jong-Woong Chang , Seong-Young Lee , Dong-Gyu Kim
发明人： Myung-Jae Park , Hyang-Shik Kong , Myung-Koo Hur , Jong-Woong Chang , Seong-Young Lee , Dong-Gyu Kim
IPC分类号： G09G3/36
CPC分类号： G02F1/13458 , G02F1/1345
摘要： A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.
摘要翻译：提供薄膜晶体管阵列面板，其包括：显示单元阵列电路，包括多个栅极线，多条数据线，多个薄膜晶体管和多个像素电极; 栅极驱动电路，向栅极线提供栅极信号; 以及连接到栅极驱动电路并且包括彼此分离的第一和第二线段的信号线以及通过至少暴露第一和第二线中的至少一个的接触孔连接到第一和第二线段的连接构件细分。

2. 发明授权

US07714820B2 Contact structure of conductive films and thin film transistor array panel including the same 有权
标题翻译：导电膜和薄膜晶体管阵列面板的接触结构包括它们
公开(公告)号：US07714820B2
公开(公告)日：2010-05-11
申请号：US10877388
申请日：2004-06-25
申请人： Myung-Jae Park , Hyang-Shik Kong , Myung-Koo Hur , Jong-Woong Chang , Seong-Young Lee , Dong-Gyu Kim
发明人： Myung-Jae Park , Hyang-Shik Kong , Myung-Koo Hur , Jong-Woong Chang , Seong-Young Lee , Dong-Gyu Kim
IPC分类号： G09G3/36
CPC分类号： G02F1/13458 , G02F1/1345
摘要： A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.
摘要翻译：提供薄膜晶体管阵列面板，其包括：显示单元阵列电路，包括多个栅极线，多条数据线，多个薄膜晶体管和多个像素电极; 栅极驱动电路，向栅极线提供栅极信号; 以及连接到栅极驱动电路并且包括彼此分离的第一和第二线段的信号线以及通过至少暴露第一和第二线中的至少一个的接触孔连接到第一和第二线段的连接构件细分。

3. 发明申请

US20090243985A1 CONTACT STRUCTURE OF CONDUCTIVE FILMS AND THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME 有权
标题翻译：导电膜和薄膜晶体管阵列的接触结构，包括它们
公开(公告)号：US20090243985A1
公开(公告)日：2009-10-01
申请号：US12407626
申请日：2009-03-19
申请人： Myung-Jae Park , Hyang-Shik Kong , Myung-Koo Hur , Jong-Woong Chang , Seong-Young Lee , Dong-Gyu Kim
发明人： Myung-Jae Park , Hyang-Shik Kong , Myung-Koo Hur , Jong-Woong Chang , Seong-Young Lee , Dong-Gyu Kim
IPC分类号： G09G3/36 , G02F1/1343 , G02F1/1333
CPC分类号： G02F1/13458 , G02F1/1345
摘要： A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.
摘要翻译：提供薄膜晶体管阵列面板，其包括：显示单元阵列电路，包括多个栅极线，多条数据线，多个薄膜晶体管和多个像素电极; 栅极驱动电路，向栅极线提供栅极信号; 以及连接到栅极驱动电路并且包括彼此分离的第一和第二线段的信号线以及通过至少暴露第一和第二线中的至少一个的接触孔连接到第一和第二线段的连接构件细分。

4. 发明申请

US20050030465A1 Contact structure of conductive films and thin film transistor array panel including the same 有权
标题翻译：导电膜和薄膜晶体管阵列面板的接触结构包括它们
公开(公告)号：US20050030465A1
公开(公告)日：2005-02-10
申请号：US10877388
申请日：2004-06-25
申请人： Myung-Jae Park , Hyang-Shik Kong , Myung-Koo Hur , Jong-Woong Chang , Seong-Young Lee , Dong-Gyu Kim
发明人： Myung-Jae Park , Hyang-Shik Kong , Myung-Koo Hur , Jong-Woong Chang , Seong-Young Lee , Dong-Gyu Kim
IPC分类号： G02F1/1345 , G02F1/1362 , G02F1/1368 , G09F9/30 , G09G3/20 , G09G3/36 , H01L21/768 , H01L23/522 , H01L29/786
CPC分类号： G02F1/13458 , G02F1/1345
摘要： A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.
摘要翻译：提供薄膜晶体管阵列面板，其包括：显示单元阵列电路，包括多个栅极线，多条数据线，多个薄膜晶体管和多个像素电极; 栅极驱动电路，向栅极线提供栅极信号; 以及连接到栅极驱动电路并且包括彼此分离的第一和第二线段的信号线以及通过至少暴露第一和第二线中的至少一个的接触孔连接到第一和第二线段的连接构件细分。

5. 发明授权

US07679596B2 Display device with reduced interference between pixels 有权
标题翻译：具有减少像素间干扰的显示设备
公开(公告)号：US07679596B2
公开(公告)日：2010-03-16
申请号：US11193975
申请日：2005-07-29
申请人： Sung-Man Kim , Jong-Hwan Lee , Seong-Young Lee , Myung-Koo Hur , Seung-Hwan Moon , Hyang-Shik Kong , Jang-Kun Song
发明人： Sung-Man Kim , Jong-Hwan Lee , Seong-Young Lee , Myung-Koo Hur , Seung-Hwan Moon , Hyang-Shik Kong , Jang-Kun Song
IPC分类号： G11C11/34
CPC分类号： G09G3/3648 , G09G3/3225 , G09G3/3266 , G09G2300/0426 , G09G2300/0465
摘要： A display device according to an exemplary embodiment of the present invention includes: a plurality of pixels including switching elements; a plurality of pairs of first and second gate lines connected to the switching elements and separated from each other, transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements, transmitting data signals, wherein each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows.
摘要翻译：根据本发明的示例性实施例的显示装置包括：包括开关元件的多个像素; 连接到开关元件并且彼此分离的多对第一和第二栅极线，传输用于接通开关元件的栅极导通电压; 以及连接到开关元件的多条数据线，发送数据信号，其中每对第一和第二栅极线设置在两个相邻的像素行之间并且连接到像素行之一。

6. 发明申请

US20060034125A1 Display device with reduced interference between pixels 有权
标题翻译：具有减少像素间干扰的显示设备
公开(公告)号：US20060034125A1
公开(公告)日：2006-02-16
申请号：US11193975
申请日：2005-07-29
申请人： Sung-Man Kim , Jong-Hwan Lee , Seong-Young Lee , Myung-Koo Hur , Seung-Hwan Moon , Hyang-Shik Kong , Jang-Kun Song
发明人： Sung-Man Kim , Jong-Hwan Lee , Seong-Young Lee , Myung-Koo Hur , Seung-Hwan Moon , Hyang-Shik Kong , Jang-Kun Song
IPC分类号： G11C11/34
CPC分类号： G09G3/3648 , G09G3/3225 , G09G3/3266 , G09G2300/0426 , G09G2300/0465
摘要： A display device according to an exemplary embodiment of the present invention includes: a plurality of pixels including switching elements; a plurality of pairs of first and second gate lines connected to the switching elements and separated from each other, transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements, transmitting data signals, wherein each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows.
摘要翻译：根据本发明的示例性实施例的显示装置包括：包括开关元件的多个像素; 连接到开关元件并且彼此分离的多对第一和第二栅极线，传输用于接通开关元件的栅极导通电压; 以及连接到开关元件的多条数据线，发送数据信号，其中每对第一和第二栅极线设置在两个相邻的像素行之间并且连接到像素行之一。

7. 发明授权

US07288442B2 Method for manufacturing contact structures of wirings 有权
标题翻译：制造接线接触结构的方法
公开(公告)号：US07288442B2
公开(公告)日：2007-10-30
申请号：US10634867
申请日：2003-08-06
申请人： Hyang-Shik Kong , Myung-Koo Hur , Chi-Woo Kim
发明人： Hyang-Shik Kong , Myung-Koo Hur , Chi-Woo Kim
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： G02F1/13439 , G02F1/13458 , H01L21/76801 , H01L21/76838 , H01L23/53209 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L2924/0002 , H01L2924/00
摘要： First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
摘要翻译：首先，将铝基材料的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。通过在大于300℃的范围内沉积氮化硅5分钟形成栅极绝缘层，并依次形成半导体层和欧姆接触层。接下来，沉积并图案化诸如Cr的金属的导体层以形成数据线，其包括与栅极线相交的数据线，源电极，漏电极和数据焊盘。然后，沉积并图案化钝化层以形成暴露漏电极，栅极焊盘和数据焊盘的接触孔。接下来，沉积并图案化氧化铟锌以形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

8. 发明申请

US20080032499A1 METHOD FOR MANUFACTURING CONTACT STRUCTURES OF WIRING 有权
标题翻译：制造接线端子结构的方法
公开(公告)号：US20080032499A1
公开(公告)日：2008-02-07
申请号：US11874769
申请日：2007-10-18
申请人： Hyang-Shik KONG , Myung-Koo Hur , Chi-Woo Kim
发明人： Hyang-Shik KONG , Myung-Koo Hur , Chi-Woo Kim
IPC分类号： H01L21/4763
CPC分类号： G02F1/13439 , G02F1/13458 , H01L21/76801 , H01L21/76838 , H01L23/53209 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L2924/0002 , H01L2924/00
摘要： First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
摘要翻译：首先，将铝基材料的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。通过在大于300℃的范围内沉积氮化硅5分钟形成栅极绝缘层，并依次形成半导体层欧姆接触层。接下来，沉积并图案化诸如Cr的金属的导体层以形成数据线，其包括与栅极线相交的数据线，源电极，漏电极和数据焊盘。然后，沉积并图案化钝化层以形成暴露漏电极，栅极焊盘和数据焊盘的接触孔。接下来，沉积并图案化氧化铟锌以形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

9. 发明授权

US07575963B2 Method for manufacturing contact structures of wiring 有权
标题翻译：制造布线接触结构的方法
公开(公告)号：US07575963B2
公开(公告)日：2009-08-18
申请号：US11874769
申请日：2007-10-18
申请人： Hyang-Shik Kong , Myung-Koo Hur , Chi-Woo Kim
发明人： Hyang-Shik Kong , Myung-Koo Hur , Chi-Woo Kim
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： G02F1/13439 , G02F1/13458 , H01L21/76801 , H01L21/76838 , H01L23/53209 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L2924/0002 , H01L2924/00
摘要： First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
摘要翻译：首先，将铝基材料的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。通过在大于300℃的范围内沉积氮化硅5分钟形成栅极绝缘层，并依次形成半导体层欧姆接触层。接下来，沉积并图案化诸如Cr的金属的导体层以形成数据线，其包括与栅极线相交的数据线，源电极，漏电极和数据焊盘。然后，沉积并图案化钝化层以形成暴露漏电极，栅极焊盘和数据焊盘的接触孔。接下来，沉积并图案化氧化铟锌以形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

10. 发明授权

US06630688B2 Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same 有权
标题翻译：布线的接触结构及其制造方法，以及包括其的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US06630688B2
公开(公告)日：2003-10-07
申请号：US09837374
申请日：2001-04-19
申请人： Hyang-Shik Kong , Myung-Koo Hur , Chi-Woo Kim
发明人： Hyang-Shik Kong , Myung-Koo Hur , Chi-Woo Kim
IPC分类号： H01L2904
CPC分类号： G02F1/13439 , G02F1/13458 , H01L21/76801 , H01L21/76838 , H01L23/53209 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L2924/0002 , H01L2924/00
摘要： First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
摘要翻译：首先，将铝基材料的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。通过在大于300℃的范围内沉积氮化硅5分钟形成栅极绝缘层，并依次形成半导体层欧姆接触层。接下来，沉积并图案化诸如Cr的金属的导体层以形成数据线，其包括与栅极线相交的数据线，源电极，漏电极和数据焊盘。然后，沉积并图案化钝化层以形成暴露漏电极，栅极焊盘和数据焊盘的接触孔。接下来，沉积并图案化氧化铟锌以形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

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