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1. 发明授权

US08203895B2 Semiconductor memory apparatus and driving method using the same 失效
标题翻译：半导体存储装置及其驱动方法
公开(公告)号：US08203895B2
公开(公告)日：2012-06-19
申请号：US12650446
申请日：2009-12-30
申请人： Myoung Jin Lee , Ki Myung Kyung
发明人： Myoung Jin Lee , Ki Myung Kyung
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C7/02
摘要： Various embodiments of a semiconductor memory apparatus and a related driving method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a switching unit and a switching control unit. The switching unit couples or decouples a cell plate voltage line to or from a cell plate electrode in response to a control signal. The switching control unit is configured to enable the control signal at a first timing and disable the control signal at a second timing.
摘要翻译：公开了半导体存储装置的各种实施例和相关的驱动方法。根据一个示例性实施例，半导体存储器设备可以包括切换单元和切换控制单元。开关单元响应于控制信号将单元板电压线与单元板电极耦合或去耦合。切换控制单元被配置为在第一定时启用控制信号，并且在第二定时禁用控制信号。

2. 发明申请

US20110075495A1 SEMICONDUCTOR MEMORY APPARATUS AND DRIVING METHOD USINGTHE SAME 失效
标题翻译：半导体存储器和驱动方法
公开(公告)号：US20110075495A1
公开(公告)日：2011-03-31
申请号：US12650446
申请日：2009-12-30
申请人： Myoung Jin Lee , Ki Myung Kyung
发明人： Myoung Jin Lee , Ki Myung Kyung
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/4074 , G11C7/02
摘要： Various embodiments of a semiconductor memory apparatus and a related driving method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a switching unit and a switching control unit. The switching unit couples or decouples a cell plate voltage line to or from a cell plate electrode in response to a control signal. The switching control unit is configured to enable the control signal at a first timing and disable the control signal at a second timing.
摘要翻译：公开了半导体存储装置的各种实施例和相关的驱动方法。根据一个示例性实施例，半导体存储器设备可以包括切换单元和切换控制单元。开关单元响应于控制信号将单元板电压线与单元板电极耦合或去耦合。切换控制单元被配置为在第一定时启用控制信号，并且在第二定时禁用控制信号。

3. 发明授权

US08369125B2 Semiconductor integrated circuit device capable of securing gate performance and channel length 有权
标题翻译：能够确保门性能和通道长度的半导体集成电路器件
公开(公告)号：US08369125B2
公开(公告)日：2013-02-05
申请号：US13087838
申请日：2011-04-15
申请人： Myoung Jin Lee
发明人： Myoung Jin Lee
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate, arranged to cross with the word lines, and delimiting a plurality of crossing regions where the word lines intersect the bit lines and a plurality of unit memory cell regions with each cell region bounded by an adjacent pair of the word lines and an adjacent pair of the bit lines; and gate electrodes for the respective unit memory cell regions, each gate electrode electrically connected with any one of a pair of word lines which delimit a corresponding unit memory cell, and formed such that at least a portion of the gate electrode is bent toward a bit line direction.
摘要翻译：半导体集成电路器件包括半导体衬底; 在半导体衬底上彼此平行延伸的多个字线; 在半导体基板上彼此平行延伸的多个位线，被布置成与字线交叉，并且限定字线与位线相交的多个交叉区域以及具有每个单元区域的多个单元存储单元区域由相邻的一对字线和相邻的一对位线限定; 以及用于各个单元存储单元区域的栅电极，每个栅电极与限定对应的单元存储单元的一对字线中的任何一个电连接，并且形成为使得栅电极的至少一部分朝向位线方向。

4. 发明授权

US08369124B2 Semiconductor memory apparatus having sense amplifier 有权
标题翻译：具有读出放大器的半导体存储装置
公开(公告)号：US08369124B2
公开(公告)日：2013-02-05
申请号：US12964182
申请日：2010-12-09
申请人： Myoung Jin Lee
发明人： Myoung Jin Lee
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C7/062
摘要： Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.
摘要翻译：公开了一种半导体存储装置，包括上层和下层，其间具有读出放大器阵列区域，其中读出放大器阵列区域包括多个读出放大器。还存在多个位线，其被配置为从上垫子朝着读出放大器阵列区域延伸，并且多个互补位线被配置为从下垫子朝着读出放大器阵列区域延伸。上层的位线和下层的互补位线被配置为在感测放大器阵列区域中以预定间隔交替布置，并且读出放大器被配置为形成在位线和相应的互补位线。

5. 发明授权

US08305823B2 Sense amplifier and semiconductor integrated circuit using the same 失效
标题翻译：感应放大器和半导体集成电路使用相同
公开(公告)号：US08305823B2
公开(公告)日：2012-11-06
申请号：US12648414
申请日：2009-12-29
申请人： Myoung Jin Lee , Hyung Sik Won
发明人： Myoung Jin Lee , Hyung Sik Won
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/062 , G11C7/08
摘要： A semiconductor integrated circuit having a sense amplifier includes first and second inverters each having an output terminal coupled to an input terminal of the other inverter. The first inverter is configured to be activated in response to a first and a third activation signals, and the second inverter is configured to be activated in response to a second and a fourth activation signals. The first and third activation signals and the second and fourth activation signals are provided through separate signal sources from each other.
摘要翻译：具有读出放大器的半导体集成电路包括第一和第二反相器，每个具有耦合到另一个反相器的输入端的输出端。第一反相器被配置为响应于第一和第三激活信号被激活，并且第二反相器被配置为响应于第二和第四激活信号被激活。第一和第三激活信号以及第二和第四激活信号通过彼此分离的信号源提供。

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