专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06097043A Semiconductor integrated circuit and supply method for supplying multiple supply voltages in a semiconductor integrated circuit 失效
标题翻译：用于在半导体集成电路中提供多个电源电压的半导体集成电路和供电方法
公开(公告)号：US06097043A
公开(公告)日：2000-08-01
申请号：US996998
申请日：1997-12-23
申请人： Mutsunori Igarashi , Hiroshi Tanaka , Kimiyoshi Usami , Takashi Ishikawa , Masahiro Kanazawa , Chiharu Mizuno
发明人： Mutsunori Igarashi , Hiroshi Tanaka , Kimiyoshi Usami , Takashi Ishikawa , Masahiro Kanazawa , Chiharu Mizuno
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L23/528 , H01L27/04 , H01L23/50
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefore in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).
摘要翻译：一种半导体集成电路，提供多个电源电压的供给方法，以及用于存储提供多个电压的供给方法的程序的记录介质，由此提供提供多个电源电压的第一单元（步骤S1），将提取的单元分成组（步骤S2），根据组的数量添加并排列用于电压供给的单元（步骤S3），并且用于供电的单元连接到用于提供多个单元的第一单元的电压通过网络供电（步骤S4）。

2. 发明授权

US06683336B1 SEMICONDUCTOR INTEGRATED CIRCUIT, SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECORD MEDIUM FOR STORING PROGRAM OF SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：用于在半导体集成电路中提供多个电源电压的半导体集成电路，供应方法和用于存储供电方法的记录介质，用于在半导体集成电路中提供多个电源电压
公开(公告)号：US06683336B1
公开(公告)日：2004-01-27
申请号：US09609408
申请日：2000-07-03
申请人： Mutsunori Igarashi , Hiroshi Tanaka , Kimiyoshi Usami , Takashi Ishikawa , Masahiro Kanazawa , Chiharu Mizuno
发明人： Mutsunori Igarashi , Hiroshi Tanaka , Kimiyoshi Usami , Takashi Ishikawa , Masahiro Kanazawa , Chiharu Mizuno
IPC分类号： H01L2710
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefor in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).
摘要翻译：提供一种半导体集成电路，提供多个电源电压的供给方法以及用于存储提供多个电压的供给方法的程序的记录介质，其中提供有多个电源电压的第一单元（步骤S1），将提取的单元分成组（步骤S2），根据组的数量添加并排列用于电压供给的单元（步骤S3），并且用于供电的单元连接到用于提供多个单元的第一单元的电压通过网络供电（步骤S4）。

3. 发明授权

US5824570A Method for designing a semiconductor integrated circuit 失效
标题翻译：半导体集成电路设计方法
公开(公告)号：US5824570A
公开(公告)日：1998-10-20
申请号：US616727
申请日：1996-03-15
申请人： Sachiko Aoki , Chiharu Mizuno
发明人： Sachiko Aoki , Chiharu Mizuno
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/02 , H01L27/04 , H01L27/118
CPC分类号： H01L27/0207 , G06F17/5068
摘要： A semiconductor integrated circuit capabling of reducing a chip area by facilitating optimization of a chip layout and a method for designing the same has been provided. For given gate level connection description, use cell information designating gates which should be designed by employing the cell patterns prepared in advance is generated. When the gate level connection description is developed into the transistor level, hybrid connection description including mixedly transistor level and gate level is then generated by employing the cell patterns relative to the gates which being designated by the use cell information and by developing gates which being not designated by the use cell information into transistor level. A layout is then designed based on the hybrid connection description including mixedly the transistor level and the gate level.
摘要翻译：已经提供了一种通过促进芯片布局优化来减少芯片面积的半导体集成电路功能及其设计方法。对于给定的门级连接描述，使用应该通过采用预先准备的单元图案来设计的小区信息指定门。当栅极电平连接描述发展成晶体管级时，然后通过采用相对于由使用单元信息指定的栅极的单元图案和通过显示不是的栅极而产生包括混合晶体管电平和栅极电平的混合连接描述由使用单元信息指定为晶体管级。然后基于混合连接描述来设计布局，包括混合晶体管电平和栅极电平。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式