专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09015112B2 Information processing device and method, program, and recording medium 有权
标题翻译：信息处理装置和方法，程序和记录介质
公开(公告)号：US09015112B2
公开(公告)日：2015-04-21
申请号：US10566472
申请日：2004-08-04
申请人： Mutsuhiro Ohmori , Tomohiro Tsunoda , Shigehiro Shimada
发明人： Mutsuhiro Ohmori , Tomohiro Tsunoda , Shigehiro Shimada
IPC分类号： G06F7/00 , H04L29/06 , G06F17/30 , G06F21/79 , G07C9/00 , G06F21/32 , G06F21/35
CPC分类号： G06F21/79 , G06F17/3074 , G06F21/32 , G06F21/35 , G07C9/00158 , H04L63/0428 , H04L63/08 , H04L63/102
摘要： To improve the convenience of a user and further provide service comfortable and safe for the user.A PK 22 storing PMD as personal related information of a user 20 communicates with a service system 24. When first using the service system 24, the PK 22 stores the service ID of the service system 24 and a spoofing preventing method. When the PK 22 communicates with the service system 24 for a second time and thereafter, a spoofing preventing process is mutually performed, and then the PMD is provided to the service system 24. The service system 24 reads or changes the PMD on the basis of access permission information set in advance by the user 20. The present invention is applicable to PDAs.
摘要翻译：为了提高用户的便利性，进一步为用户提供舒适，安全的服务。存储PMD作为用户20的个人信息的PK22与服务系统24通信。当首次使用服务系统24时，PK 22存储服务系统24的服务ID和防止欺骗的方法。当PK 22第二次与服务系统24进行通信之后，相互执行防止欺骗处理，然后将PMD提供给服务系统24.服务系统24基于以下方式读取或改变PMD：用户20预先设定的访问许可信息。本发明适用于PDA。

2. 发明申请

US20060200467A1 Information processing device and method, program, and recording medium 有权
公开(公告)号：US20060200467A1
公开(公告)日：2006-09-07
申请号：US10566472
申请日：2004-08-04
申请人： Mutsuhiro Ohmori , Tomohiro Tsunoda , Shigehiro Shimada
发明人： Mutsuhiro Ohmori , Tomohiro Tsunoda , Shigehiro Shimada
IPC分类号： G06F17/30
CPC分类号： G06F21/79 , G06F17/3074 , G06F21/32 , G06F21/35 , G07C9/00158 , H04L63/0428 , H04L63/08 , H04L63/102
摘要： To improve the convenience of a user and further provide service comfortable and safe for the user. A PK 22 storing PMD as personal related information of a user 20 communicates with a service system 24. When first using the service system 24, the PK 22 stores the service ID of the service system 24 and a spoofing preventing method. When the PK 22 communicates with the service system 24 for a second time and thereafter, a spoofing preventing process is mutually performed, and then the PMD is provided to the service system 24. The service system 24 reads or changes the PMD on the basis of access permission information set in advance by the user 20. The present invention is applicable to PDAs.

3. 发明授权

US07583270B2 Image processing apparatus 有权
公开(公告)号：US07583270B2
公开(公告)日：2009-09-01
申请号：US09789597
申请日：2001-02-22
申请人： Mutsuhiro Ohmori , Toshio Horioka
发明人： Mutsuhiro Ohmori , Toshio Horioka
IPC分类号： G06F12/00
CPC分类号： G06T15/005
摘要： An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a decline in the performance is not caused. A built-in DRAM inside a semiconductor chip has a configuration for storing display data and the texture data required by at least one graphic element. The texture data can be stored in portions other than the display regions, so the built-in DRAM can be used efficiently and an image processing apparatus achieving both high speed operation and a reduction of power consumption can be realized.

4. 发明申请

US20080104366A1 Semiconductor chip 有权
标题翻译：半导体芯片
公开(公告)号：US20080104366A1
公开(公告)日：2008-05-01
申请号：US11898241
申请日：2007-09-11
申请人： Mutsuhiro Ohmori
发明人： Mutsuhiro Ohmori
IPC分类号： G06F15/80
CPC分类号： G06F15/8015 , G06F11/2038 , G06F11/2043
摘要： Disclosed herein is a semiconductor chip including at least two processing apparatuses which comply with the same interface specifications and which differ in internal structure, wherein at least one of the processing apparatuses is constituted functionally to replace at least one processing apparatus.
摘要翻译：本文公开了一种半导体芯片，其包括至少两个符合相同接口规范并且内部结构不同的处理装置，其中至少一个处理装置在功能上构成以代替至少一个处理装置。

5. 发明申请

US20080071996A1 Shared memory device 有权
标题翻译：共享内存设备
公开(公告)号：US20080071996A1
公开(公告)日：2008-03-20
申请号：US11892722
申请日：2007-08-27
申请人： Mutsuhiro Ohmori , Motofumi Kashiwaya
发明人： Mutsuhiro Ohmori , Motofumi Kashiwaya
IPC分类号： G06F13/14
CPC分类号： G06F13/4022
摘要： A shared memory device is disclosed which includes: a plurality of processor elements; a plurality of memory modules configured to be accessible by the plurality of processor elements; and a connection device configured to enable a specific processor element out of the plurality of processor elements to access a specific memory module out of the plurality of memory modules; wherein the plurality of processor elements are allowed to access via the connection device a plurality of memory systems each constituted by at least one memory module; and wherein each of the plurality of memory systems accessible by different processor elements allows the plurality of memory modules to be partially shared and accessed by the different processor elements.
摘要翻译：公开了一种共享存储器件，其包括：多个处理器元件; 多个存储器模块，被配置为可被所述多个处理器元件访问; 以及连接装置，被配置为使得所述多个处理器元件中的特定处理器元件能够访问所述多个存储器模块中的特定存储器模块; 其中所述多个处理器元件被允许经由所述连接装置访问各自由至少一个存储器模块构成的多个存储器系统; 并且其中由不同处理器元件访问的多个存储器系统中的每一个允许所述多个存储器模块被不同的处理器元件部分地共享和访问。

6. 发明授权

US06992664B2 Graphics plotting apparatus 失效
标题翻译：图形绘图仪
公开(公告)号：US06992664B2
公开(公告)日：2006-01-31
申请号：US09796901
申请日：2001-02-28
申请人： Mutsuhiro Ohmori
发明人： Mutsuhiro Ohmori
IPC分类号： G06T15/00 , G06T13/14 , G09G5/00
CPC分类号： G09G5/39 , G09G5/363
摘要： A graphics plotting apparatus which can realize both optimum division of a processing system into blocks and optimum arrangement of the blocks and can be augmented in terms of the performance for a three-dimensional graphics plotting process. The graphics plotting apparatus includes a logic circuit block and a memory block having a capacity sufficient to store display data to be displayed. Both blocks are built in the same chip. An input buffer having a capacity for more than one apex of a three-dimensional graphics plotting primitive is provided, and an interface for transfer of data to and from the outside and the input buffer are arranged on one side of the logic circuit block. A DDA setup circuit is arranged adjacent the input buffer, and a triangle DDA circuit is arranged adjacent the DDA setup circuit. A pair of texture processing circuit blocks are arranged adjacent the triangle DDA circuit. The block sizes of the texture processing circuit blocks are set greater than those of the DDA setup circuit and the triangle DDA circuit.
摘要翻译：可以实现将处理系统最佳划分为块和块的最佳布置的图形绘图装置，并且可以在三维图形绘制过程的性能方面得到增强。图形绘制装置包括逻辑电路块和具有足以存储要显示的显示数据的能力的存储块。两块都是在同一个芯片内置的。提供具有三维图形绘制原语的多于一个顶点的容量的输入缓冲器，并且用于将数据传送到外部和从外部传送数据的接口和输入缓冲器布置在逻辑电路块的一侧。 DDA设置电路邻近输入缓冲器布置，三角形DDA电路设置在DDA设置电路附近。一对纹理处理电路块被布置在三角形DDA电路附近。纹理处理电路块的块大小被设置为大于DDA设置电路和三角形DDA电路的块大小。

7. 发明申请

US20120185859A1 METHODS AND SYSTEMS FOR PROGRAM ANALYSIS AND PROGRAM CONVERSION 审中-公开
标题翻译：程序分析和程序转换的方法和系统
公开(公告)号：US20120185859A1
公开(公告)日：2012-07-19
申请号：US13389134
申请日：2010-08-05
申请人： Motofumi Kashiwaya , Mutsuhiro Ohmori , Kurniawan Warih
发明人： Motofumi Kashiwaya , Mutsuhiro Ohmori , Kurniawan Warih
IPC分类号： G06F9/46
CPC分类号： G06F9/3832 , G06F9/30076 , G06F9/3808 , G06F9/381
摘要： History memory 430 correlates the input values and execution result of a function for each piece of function identification information, and holds as an execution history. A command decoder 320 supplies function identification information included in a previous notice command for predicting the function from a fetch unit 310 to an execution history search unit 410. Also, the command decoder 320 causes the execution history search unit 410 to obtain the input value output from an input selecting unit 332 based on, of commands to be read out after the previous notice command, an input value setting command for setting a function input value. The execution history search unit 410 searches an execution history agreeing with the obtained identification information and input values thereof before a function call-up command. An execution result output unit 420 outputs the execution result detected by the execution history search unit 410 to an executing unit 330. The fetch unit 310 reads out a command to be read out following the function.
摘要翻译：历史存储器430将每个功能识别信息的功能的输入值和执行结果相关联，并保持为执行历史。命令解码器320将包括在先前通知命令中的功能识别信息提供给执行历史搜索单元410.此外，命令解码器320使得执行历史搜索单元410获得输入值输出从输入选择单元332基于在先前通知命令之后要读出的命令，输入用于设置功能输入值的输入值设置命令。执行历史搜索单元410在功能调用命令之前搜索与获得的识别信息一致的执行历史及其输入值。执行结果输出单元420将由执行历史搜索单元410检测到的执行结果输出到执行单元330.读取单元310读出在该功能之后要读出的命令。

8. 发明申请

US20090150651A1 Semiconductor chip 有权
标题翻译：半导体芯片
公开(公告)号：US20090150651A1
公开(公告)日：2009-06-11
申请号：US12292310
申请日：2008-11-17
申请人： Mutsuhiro Ohmori
发明人： Mutsuhiro Ohmori
IPC分类号： G06F1/26 , G06F9/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： Disclosed herein is a semiconductor chip including: a plurality of processing devices that can communicate with each other; wherein each of the processing devices includes an arithmetic unit, an individual memory connected to the arithmetic unit on a one-to-one basis, and a control unit configured to independently control turning on and off of operation of the arithmetic unit and the individual memory.
摘要翻译：这里公开了一种半导体芯片，包括：能够彼此通信的多个处理装置; 其中每个所述处理装置包括运算单元，一对一连接到所述运算单元的单独存储器，以及控制单元，被配置为独立地控制所述运算单元和所述单独存储器的运行的导通和关断。

9. 发明授权

US07411412B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07411412B2
公开(公告)日：2008-08-12
申请号：US11499730
申请日：2006-08-07
申请人： Tomofumi Arakawa , Mutsuhiro Ohmori
发明人： Tomofumi Arakawa , Mutsuhiro Ohmori
IPC分类号： H03K19/003 , G06F7/38
CPC分类号： H03K19/00392
摘要： A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number of modules and R number of I/O parts of the circuit block and connecting one module selected from among at least two modules to each of the R number of I/O parts. Each of the R number of I/O parts has a data holding part for holding a function setting data and inputting the held function setting data to the destination module, and N modules are able to replace functions of each other when the input function setting data are the same.
摘要翻译：一种半导体集成电路，包括：根据输入功能设置数据设置其功能的N个模块，具有R个I / O部分的电路块，以及用于从N个模块中选择R个模块的模块选择部分连接所选择的R个模块和R个电路块的I / O部分，并将从至少两个模块中选出的一个模块连接到R个I / O部分中的每一个。 R个I / O部分中的每一个具有用于保持功能设置数据并将保持的功能设置数据输入到目的地模块的数据保持部分，并且当输入功能设置数据时，N个模块能够替换彼此的功能是相同的。

10. 发明申请

US20070057690A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20070057690A1
公开(公告)日：2007-03-15
申请号：US11499730
申请日：2006-08-07
申请人： Tomofumi Arakawa , Mutsuhiro Ohmori
发明人： Tomofumi Arakawa , Mutsuhiro Ohmori
IPC分类号： H03K19/003
CPC分类号： H03K19/00392
摘要： A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number of modules and R number of I/O parts of the circuit block and connecting one module selected from among at least two modules to each of the R number of I/O parts. Each of the R number of I/O parts has a data holding part for holding a function setting data and inputting the held function setting data to the destination module, and N modules are able to replace functions of each other when the input function setting data are the same.
摘要翻译：一种半导体集成电路，包括：根据输入功能设置数据设置其功能的N个模块，具有R个I / O部分的电路块，以及用于从N个模块中选择R个模块的模块选择部分连接所选择的R个模块和R个电路块的I / O部分，并将从至少两个模块中选出的一个模块连接到R个I / O部分中的每一个。 R个I / O部分中的每一个具有用于保持功能设置数据并将保持的功能设置数据输入到目的地模块的数据保持部分，并且当输入功能设置数据时，N个模块能够替换彼此的功能是相同的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式