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1. 发明授权

US06284666B1 Method of reducing RIE lag for deep trench silicon etching 失效
标题翻译：减少深沟槽硅蚀刻RIE滞后的方法
公开(公告)号：US06284666B1
公开(公告)日：2001-09-04
申请号：US09583963
申请日：2000-05-31
申请人： Munir D. Naeem , Gangadhara S. Mathad , Byeong Yeol Kim , Stephan P. Kudelka , Brian S. Lee , Heon Lee , Elizabeth Morales , Young-Jin Park , Rajiv M. Ranade
发明人： Munir D. Naeem , Gangadhara S. Mathad , Byeong Yeol Kim , Stephan P. Kudelka , Brian S. Lee , Heon Lee , Elizabeth Morales , Young-Jin Park , Rajiv M. Ranade
IPC分类号： H01L21302
CPC分类号： H01L21/3081 , H01L21/3065
摘要： A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e.,
摘要翻译：最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， <30：1）。该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。或者，通过非RIE蚀刻工艺去除钝化膜。可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。膜的受控厚度允许实现高纵横比结构的预定DT深度。

2. 发明授权

US06939763B2 DRAM cell arrangement with vertical MOS transistors, and method for its fabrication 失效
标题翻译：具有垂直MOS晶体管的DRAM单元布置及其制造方法
公开(公告)号：US06939763B2
公开(公告)日：2005-09-06
申请号：US10720730
申请日：2003-11-24
申请人： Till Schlösser , Brian S. Lee
发明人： Till Schlösser , Brian S. Lee
IPC分类号： H01L21/02 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/786
CPC分类号： H01L27/10858 , H01L27/10852 , H01L27/10876
摘要： DRAM cell arrangement with vertical MOS transistors, and method for its fabrication. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.
摘要翻译：具有垂直MOS晶体管的DRAM单元布置及其制造方法。沿着存储单元矩阵的一列排列的通道区域是由栅介质层包围的肋的部分。属于一行的MOS晶体管的栅电极是条状字线的一部分，因此在存储单元矩阵的每个交叉点存在垂直双栅极MOS晶体管，其中形成相关联的字线的栅电极相关肋骨两侧的沟槽。

3. 发明申请

US20100103717A1 TUNING A VARIABLE RESISTANCE OF A RESISTIVE SENSE ELEMENT 有权
标题翻译：调整电阻感知元件的可变电阻
公开(公告)号：US20100103717A1
公开(公告)日：2010-04-29
申请号：US12497929
申请日：2009-07-06
申请人： Brian S. Lee , Haiwen Xi , Patrick J. Ryan , Rod Bowman
发明人： Brian S. Lee , Haiwen Xi , Patrick J. Ryan , Rod Bowman
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C7/06 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C29/026 , G11C29/028 , G11C29/50008 , G11C2013/0073 , G11C2207/2254 , G11C2213/31
摘要： Method and apparatus for tuning a variable resistance resistive sense element of an electronic device. In some embodiments, a value indicative of a selected number of consecutive pulses is stored in a memory location and a resistive sense element (RSE) is set to a baseline RSE resistance. A tuning operation is performed by applying the selected number of consecutive pulses to the RSE to tune the baseline RSE resistance to a final adjusted resistance.
摘要翻译：用于调谐电子设备的可变电阻电阻感测元件的方法和装置。在一些实施例中，将指示所选数量的连续脉冲的值存储在存储器位置中，并且将电阻感测元件（RSE）设置为基线RSE电阻。通过将所选数量的连续脉冲施加到RSE来执行调谐操作，以将基线RSE电阻调谐到最终调整的电阻。

4. 发明授权

US06372567B1 Control of oxide thickness in vertical transistor structures 有权
标题翻译：垂直晶体管结构中氧化物厚度的控制
公开(公告)号：US06372567B1
公开(公告)日：2002-04-16
申请号：US09553708
申请日：2000-04-20
申请人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening
发明人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening
IPC分类号： H01L218238
CPC分类号： H01L21/28211 , H01L21/2236 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/28238 , H01L27/10864 , H01L27/10873 , H01L29/045
摘要： Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.
摘要翻译：在DRAM中制备垂直晶体管结构的改进方法，其中沟槽顶部氧化物将底部存储电容器与开关晶体管分离，并且其中沟槽的上部在其侧壁处包含垂直晶体管，以获得均匀的栅极氧化沟槽内的所有不同的晶面，使得均匀的厚度与晶体取向无关，包括：a）使晶片沟槽侧壁进行离子轰击足以产生氧化物侧壁的非晶层的时间; 和b）在氧化气氛中加热由步骤（a）得到的晶片，以引起非晶层的氧化和重结晶。

5. 发明授权

US07087947B2 Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same 有权
标题翻译：具有环线图案结构的半导体器件，用于制造其的交替相移掩模
公开(公告)号：US07087947B2
公开(公告)日：2006-08-08
申请号：US10957688
申请日：2004-10-05
申请人： Brian S. Lee , Chih-Yu Lee
发明人： Brian S. Lee , Chih-Yu Lee
IPC分类号： H01L27/108
CPC分类号： H01L21/32139 , G03F1/30 , H01L27/10861 , H01L27/10891
摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.
摘要翻译：具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区域或栅极线。通过使用交替相移掩模来对DRAM阵列中的栅极线或有源区进行图案化，在DRAM阵列中不产生不需要的图像，并且仅需要一次曝光来实现高分辨率要求。

6. 发明授权

US06544888B2 Advanced contact integration scheme for deep-sub-150 nm devices 有权
标题翻译：深层次的150纳米器件的高级接触集成方案
公开(公告)号：US06544888B2
公开(公告)日：2003-04-08
申请号：US09892620
申请日：2001-06-28
申请人： Brian S. Lee
发明人： Brian S. Lee
IPC分类号： H01L2144
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/823871
摘要： An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes with a process employing a W-Salicide combined with ion mixing implantation. The contact integration technique realizes junctions having low contact resistance (RC), with ultra-shallow contact junction depth (XJC) and high doping concentration in the silicide contact interface (Nc).
摘要翻译：用于深 - 150nm半导体器件（例如W / WN栅电极，双功函数栅极，双栅MOSFET和SOI器件）的先进接触积分技术。该技术将自对准凸起源极/漏极接触过程与采用W-Salicide结合离子混合植入的方法相结合。接触积分技术实现了具有低接触电阻（RC）的接点，具有超浅接触结深度（XJC）和硅化物接触界面（Nc）中的高掺杂浓度。

7. 发明授权

US06426253B1 Method of forming a vertically oriented device in an integrated circuit 有权
标题翻译：在集成电路中形成垂直取向器件的方法
公开(公告)号：US06426253B1
公开(公告)日：2002-07-30
申请号：US09576465
申请日：2000-05-23
申请人： Helmut Horst Tews , Alexander Michaelis , Brian S. Lee , Uwe Schroeder , Stephan Kudelka
发明人： Helmut Horst Tews , Alexander Michaelis , Brian S. Lee , Uwe Schroeder , Stephan Kudelka
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/76237 , H01L21/823487 , H01L27/10841 , H01L27/10867
摘要： A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.
摘要翻译：使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或在沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分沟槽暴露进一步加工。或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

8. 发明授权

US06362040B1 Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates 失效
标题翻译：减少半导体衬底的垂直侧壁的取向依赖氧化
公开(公告)号：US06362040B1
公开(公告)日：2002-03-26
申请号：US09501502
申请日：2000-02-09
申请人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening , Raj Jammy , John Faltermeier
发明人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening , Raj Jammy , John Faltermeier
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L27/10876
摘要： A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer. The second dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness and the second thickness of the second dielectric layer are closer in thickness than the first thickness and the second thickness of the first dielectric layer due to the implantation of the dopants.
摘要翻译：根据本发明的用于在衬底上生长电介质层的方法包括以下步骤：提供具有至少两个结晶面的衬底，所述晶体面由于至少两个晶面而具有不同的介电层生长速率。在至少两个晶面上生长第一介电层，使得第一介电层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。第一厚度比第一电介质层的第二厚度厚。通过第一介电层注入掺杂剂。通过第二厚度将更多数量的掺杂剂注入到衬底中，而不是通过第一介电层的第一厚度。然后去除第一介电层。在与去除的第一介电层相同的位置处生长第二介电层。第二电介质层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。由于掺杂剂的注入，第二介电层的第一厚度和第二厚度比第一厚度和第一介电层的第二厚度更厚。

9. 发明授权

US06335247B1 Integrated circuit vertical trench device and method of forming thereof 有权
标题翻译：集成电路垂直沟槽器件及其形成方法
公开(公告)号：US06335247B1
公开(公告)日：2002-01-01
申请号：US09597389
申请日：2000-06-19
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Brian S. Lee
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Brian S. Lee
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10876
摘要： A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.
摘要翻译：一种使用选择性湿蚀刻在集成电路中形成垂直取向器件的方法，以仅去除深沟槽中的一部分侧壁，以及由此形成的器件。虽然沟槽周边的一部分（例如，隔离环304）被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的衬底侧壁（324）与单晶面。单侧垂直沟槽晶体管可以形成在平坦侧壁上。形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。

10. 发明授权

US06207573B1 Differential trench open process 有权
标题翻译：差分沟开放过程
公开(公告)号：US06207573B1
公开(公告)日：2001-03-27
申请号：US09314358
申请日：1999-05-19
申请人： Brian S. Lee
发明人： Brian S. Lee
IPC分类号： H01L21311
CPC分类号： H01L21/0332 , H01L21/3081 , H01L21/31144
摘要： In accordance with the invention, a method for opening holes for semiconductor fabrication includes the steps of providing a pad stack on a substrate, forming a hard mask layer on the pad stack, the hard mask layer selectively removable relative to the pad stack, patterning a resist layer on the hard mask layer, the resist layer being selectively removable relative to the hard mask layer and having a thickness sufficient to prevent scalloping, etching the hard mask layer selective to the resist layer down to the pad stack, removing the resist layer. After removing the resist layer, the pad stack is etched selective to the hard mask layer such that a hole is opened down to the substrate.
摘要翻译：根据本发明，一种用于半导体制造的开孔的方法包括以下步骤：在衬底上提供衬垫堆叠，在衬垫堆叠上形成硬掩模层，相对于衬垫叠层选择性地可去除的硬掩模层，图案化抗蚀剂层相对于硬掩模层可选择性地去除，并且具有足以防止扇形化的厚度，将对抗蚀剂层选择性的硬掩模层蚀刻到焊盘堆叠，去除抗蚀剂层。在去除抗蚀剂层之后，对硬掩模层选择性地蚀刻焊盘叠层，使得孔向下打开到基板。

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