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1. 发明授权

US07566637B2 Method of inhibition of metal diffusion arising from laser dicing 失效
标题翻译：抑制激光切割引起的金属扩散的方法
公开(公告)号：US07566637B2
公开(公告)日：2009-07-28
申请号：US11955484
申请日：2007-12-13
申请人： Mukta G Farooq , Robert Hannon , Dae-Young Jung
发明人： Mukta G Farooq , Robert Hannon , Dae-Young Jung
IPC分类号： H01L21/304
CPC分类号： H01L21/02076
摘要： Method of inhibiting metal diffusion arising from laser dicing is provided. The method includes dividing a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the method exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment includes a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch may be performed on the chip.
摘要翻译：提供了抑制激光切割引起的金属扩散的方法。该方法包括将晶片分成至少一个芯片。该芯片包括内部金属特征。分散在芯片的外表面上沉积至少一种金属物质。在分割芯片之后，该方法将芯片暴露于具有给定压力（例如，小于一个大气压）的加热的环境环境中。环境包括能够与金属物质结合的化学试剂。另外，可以在芯片上进行湿式化学蚀刻。

2. 发明授权

US08487425B2 Optimized annular copper TSV 有权
标题翻译：优化环形铜TSV
公开(公告)号：US08487425B2
公开(公告)日：2013-07-16
申请号：US13167107
申请日：2011-06-23
申请人： Paul S Andry , Mukta G Farooq , Robert Hannon , Subramanian S Iyer , Emily R Kinser , Cornelia K Tsang , Richard P Volant
发明人： Paul S Andry , Mukta G Farooq , Robert Hannon , Subramanian S Iyer , Emily R Kinser , Cornelia K Tsang , Richard P Volant
IPC分类号： H01L23/04 , H01L23/48
CPC分类号： H01L21/76846 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.
摘要翻译：本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。基板厚度可以为60微米或更小。具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

3. 发明授权

US08859390B2 Structure and method for making crack stop for 3D integrated circuits 有权
标题翻译：三维集成电路裂纹停止的结构和方法
公开(公告)号：US08859390B2
公开(公告)日：2014-10-14
申请号：US12700841
申请日：2010-02-05
申请人： Mukta G Farooq , John A Griesemer , William F Landers , Ian D Melville , Thomas M Shaw , Huilong Zhu
发明人： Mukta G Farooq , John A Griesemer , William F Landers , Ian D Melville , Thomas M Shaw , Huilong Zhu
IPC分类号： H01L23/58 , H01L25/065 , H01L21/78 , H01L23/48 , H01L23/00 , H01L21/768 , H01L23/31 , H01L21/20
CPC分类号： H01L23/5226 , H01L21/2007 , H01L21/76898 , H01L21/78 , H01L23/3114 , H01L23/481 , H01L23/53214 , H01L23/53228 , H01L23/562 , H01L23/585 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.
摘要翻译：公开了一种用于防止裂纹传播到3D集成电路的有源区域的结构，例如由薄化的衬底层或接合层的外围处的缺陷引发的裂纹及其形成方法。

4. 发明授权

US08237288B1 Enhanced electromigration resistance in TSV structure and design 有权
公开(公告)号：US08237288B1
公开(公告)日：2012-08-07
申请号：US13023743
申请日：2011-02-09
申请人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

5. 发明授权

US08853857B2 3-D integration using multi stage vias 有权
标题翻译：使用多级通孔的3-D集成
公开(公告)号：US08853857B2
公开(公告)日：2014-10-07
申请号：US13101268
申请日：2011-05-05
申请人： Mukta G Farooq , Troy L Graves-Abe
发明人： Mukta G Farooq , Troy L Graves-Abe
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.
摘要翻译：可以形成TSV，其具有通过顶部衬底表面形成的顶部截面，以及通过底部衬底表面形成的底部截面。顶部截面可以具有对应于设计规则的最小横截面，并且顶部截面深度可以对应于可工作的纵横比。顶部通孔可以被填充或插入，以便可以继续顶部处理。底部通孔可以具有更大的横截面，以便于形成穿过其中的导电路径。底部部分通孔从顶部部分通孔的背面延伸到底部，并且在基板变薄之后形成。可以通过在从接合的顶部和底部部分通孔去除牺牲填充材料之后形成导电路径来完成TSV。

6. 发明授权

US07731077B2 Structure and method to gain substantial reliability improvements in lead-free BGAs assembled with lead-bearing solders 失效
标题翻译：结构和方法可以在与含铅焊料组装的无铅BGA中获得显着的可靠性改进
公开(公告)号：US07731077B2
公开(公告)日：2010-06-08
申请号：US11759298
申请日：2007-06-07
申请人： Mukta G Farooq , Charles C Goldsmith
发明人： Mukta G Farooq , Charles C Goldsmith
IPC分类号： B23K31/02
CPC分类号： B23K3/0638 , B23K2101/40 , H05K3/3436 , H05K3/3463 , H05K2201/10992 , Y02P70/613 , Y10T29/49149
摘要： Methods of forming and assemblies having hybrid interconnection grid arrays composed of a homogenous mixture of Pb-free solder joints and Pb-containing solder paste on corresponding sites of a printed board. The aligned Pb-free solder joints and Pb-containing solders are heated to a temperature above a melting point of the Pb-free solder joint for a sufficient time to allow complete melting of both the Pb-free solder joints and Pb-containing solder paste and the homogenous mixing thereof during assembly. These molten materials mix together such that the Pb from the Pb-containing solder disperses throughout substantially the entire Pb-free solder joint for complete homogenization of the molten materials to form the homogenous hybrid interconnect structures of the invention.
摘要翻译：具有混合互连栅格阵列的形成和组装方法，其由印刷电路板的相应位置上的无铅焊点和含Pb焊膏的均匀混合物组成。将排列的无铅焊点和含Pb焊料加热到无铅焊点的熔点以上的温度足够的时间，以使无铅焊点和含Pb焊膏完全熔化并在组装期间均匀混合。这些熔融材料混合在一起，使得来自含Pb焊料的Pb分散在基本上整个无铅焊料接头处，以使熔融材料完全均化，形成本发明的均匀混合互连结构。

7. 发明授权

US08492241B2 Method for simultaneously forming a through silicon via and a deep trench structure 有权
标题翻译：同时形成硅通孔和深沟槽结构的方法
公开(公告)号：US08492241B2
公开(公告)日：2013-07-23
申请号：US12904348
申请日：2010-10-14
申请人： Kangguo Cheng , Mukta G Farooq , Louis L Hsu
发明人： Kangguo Cheng , Mukta G Farooq , Louis L Hsu
IPC分类号： H01L21/8249 , H01L21/76
CPC分类号： H01L27/0207 , G06F17/5081 , H01L21/743 , H01L21/76898
摘要： A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.
摘要翻译：通过单个掩模和单个反应离子蚀刻（RIE）同时在同一衬底上形成贯通硅通孔（TSV）和深沟槽电容器（DTCap）或深沟槽隔离（DTI）。 TSV沟槽比DTCap或DTI沟槽更宽更深。 TSV和DTCap或DTI在沟槽侧壁上形成有不同的介电材料。 TSV和DTCap或DTI完全对齐。

8. 发明授权

US08476168B2 Non-conformal hardmask deposition for through silicon etch 有权
标题翻译：用于通过硅蚀刻的非保形硬掩模沉积
公开(公告)号：US08476168B2
公开(公告)日：2013-07-02
申请号：US13014114
申请日：2011-01-26
申请人： Troy L. Graves-Abe , Mukta G Farooq
发明人： Troy L. Graves-Abe , Mukta G Farooq
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/76898
摘要： The present invention provides a method to form deep features in a stacked semiconductor structure. Deposition of a non-conformal hardmask onto a patterned topography can form a hardmask to protect all but recessed areas with minimal integration steps. The invention enables etching deep features, even through multiple BEOL layers, without multiple additional process steps.
摘要翻译：本发明提供一种在堆叠半导体结构中形成深层特征的方法。将非保形硬掩模沉积到图案化地形上可以形成硬掩模，以最小的集成步骤来保护所有凹陷区域。本发明即使通过多个BEOL层也能够蚀刻深层特征，而不需要多个额外的工艺步骤。

9. 发明授权

US08288270B2 Enhanced electromigration resistance in TSV structure and design 有权
标题翻译： TSV结构和设计中增强的电迁移阻力
公开(公告)号：US08288270B2
公开(公告)日：2012-10-16
申请号：US13397004
申请日：2012-02-15
申请人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
发明人： Mukta G Farooq , John A Griesemer , Gary LaFontant , William Francis Landers , Timothy Dooling Sullivan
IPC分类号： H01L21/4763
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.
摘要翻译：这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

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