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1. 发明申请

US20140007031A1 SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：半导体器件设计方法，系统和计算机程序产品
公开(公告)号：US20140007031A1
公开(公告)日：2014-01-02
申请号：US13539258
申请日：2012-06-29
申请人： Mu-Jen HUANG , Chih Chi HSIAO , Wei-Ting LIN , Tsung-Hsin YU , Chien-Wen CHEN , Yung-Chow PENG
发明人： Mu-Jen HUANG , Chih Chi HSIAO , Wei-Ting LIN , Tsung-Hsin YU , Chien-Wen CHEN , Yung-Chow PENG
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5077 , G06F17/5081
摘要： In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.
摘要翻译：在由至少一个处理器执行的半导体器件设计方法中，所述至少一个处理器提取半导体器件的布局中的至少一个电气部件的位置数据。由至少一个处理器提取与所述至少一个电气部件相关联并且基于所述半导体器件的操作的模拟的电压数据。基于所提取的位置数据，所提取的电压数据由所述至少一个处理器并入所述布局中以生成所述半导体器件的修改的布局。

2. 发明申请

US20130326447A1 METHOD AND SYSTEM FOR LAYOUT PARASITIC ESTIMATION 有权
标题翻译：用于布局PARASITIC估计的方法和系统
公开(公告)号：US20130326447A1
公开(公告)日：2013-12-05
申请号：US13484480
申请日：2012-05-31
申请人： Mu-Jen HUANG , Yu-Sian JIANG , Yi-Ting LIN , Hsien-Yu TSENG , Heng Kai LIU , Chien-Wen CHEN , Chauchin SU
发明人： Mu-Jen HUANG , Yu-Sian JIANG , Yi-Ting LIN , Hsien-Yu TSENG , Heng Kai LIU , Chien-Wen CHEN , Chauchin SU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82
摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.
摘要翻译：一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。

3. 发明申请

US20130320555A1 EDA TOOL AND METHOD, AND INTEGRATED CIRCUIT FORMED BY THE METHOD 有权
标题翻译： EDA工具和方法，以及通过该方法形成的集成电路
公开(公告)号：US20130320555A1
公开(公告)日：2013-12-05
申请号：US13484488
申请日：2012-05-31
申请人： Hsien YU-TSENG , Shih-Kai LIN , Chin-Shen LIN , Yu-Sian JIANG , Heng-Kai LIU , Mu-Jen HUANG , Chien-Wen CHEN
发明人： Hsien YU-TSENG , Shih-Kai LIN , Chin-Shen LIN , Yu-Sian JIANG , Heng-Kai LIU , Mu-Jen HUANG , Chien-Wen CHEN
IPC分类号： H01L27/00 , G06F17/50
CPC分类号： H01L23/528 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L21/76816 , H01L23/53228 , H01L27/0207
摘要： A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.
摘要翻译：一种方法包括：访问表示集成电路（IC）的层的布局的数据，所述集成电路的层包括多个多边形，所述多边形限定电路图案，以划分数个（N）个光掩模，用于多个图案化半导体衬底的单层; 其中N大于1。对于布局中的每个N个平行多边形组合，彼此比用用于单一光掩模进行图案化的最小间隔更靠近，在该组内的每个多边形中插入至少N-1个针脚，以将每个多边形分成至少N个部分，例如不同多边形的相邻部分被分配给彼此不同的光掩模。表示将每个组中的每个部分分配给相应光掩模的数据被存储在非瞬时的计算机可读存储介质中，该介质可访问以用于制造N个光掩模的过程。

4. 发明申请

US20140068540A1 INTEGRATED CIRCUIT DESIGN FLOW WITH LAYOUT-DEPENDENT EFFECTS 有权
标题翻译：集成电路设计流程，具有布局依赖性的影响
公开(公告)号：US20140068540A1
公开(公告)日：2014-03-06
申请号：US13601773
申请日：2012-08-31
申请人： Mu-Jen HUANG , Yu-Sian JIANG , Chien-Wen CHEN
发明人： Mu-Jen HUANG , Yu-Sian JIANG , Chien-Wen CHEN
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5009 , G06F17/5081
摘要： A design system for designing an integrated circuit that includes a processor, a memory coupled to the processor, and instructions to generate and edit a schematic of the integrated circuit, generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit, extract the at least one recommended layout parameter during a layout stage of the integrated circuit, and calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter, and a user interface configured to display at least one of the circuit performance parameter and layout constraints of the integrated circuit device of the integrated circuit.
摘要翻译：一种用于设计包括处理器，耦合到处理器的存储器和用于生成和编辑集成电路的原理图的指令的集成电路的设计系统，生成集成电路内的集成电路器件的至少一个推荐布局参数，在所述集成电路的布局阶段期间提取所述至少一个推荐的布局参数，以及使用所述至少一个推荐布局参数来计算所述集成电路的电路性能参数;以及用户界面，被配置为显示所述电路性能中的至少一个集成电路集成电路器件的参数和布局约束。

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