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1. 发明授权

US5469543A Policing circuits arranged in matrix array for selectively transferring virtual path identifier (VPI) responsive to either VPI or service class identifier (SCI) threshold value 失效
标题翻译：布置在矩阵阵列中的监管电路，用于响应于VPI或服务类别标识符（SCI）阈值选择性地传送虚拟路径标识符（VPI）
公开(公告)号：US5469543A
公开(公告)日：1995-11-21
申请号：US931039
申请日：1992-08-14
申请人： Motoo Nishihara , Takatoshi Kurano , Naoaki Yamanaka , Youichi Sato
发明人： Motoo Nishihara , Takatoshi Kurano , Naoaki Yamanaka , Youichi Sato
IPC分类号： H04Q11/04 , H04L12/813 , H04L12/823 , H04L12/863 , H04Q3/00 , G06F7/02 , G06F7/04 , G06F7/10
CPC分类号： H04L12/5602 , H04L49/309 , H04L2012/5614 , H04L2012/5619 , H04L2012/5636
摘要： In a policing arrangement for an ATM network, every incoming cell is stored in a cell buffer and a virtual path identifier (VPI) contained in the cell is extracted and translated to a corresponding one of a set of threshold values. Policing circuits of a matrix array are connected column by column for transferring a VPI in accordance with a read/write control circuit. Each policing circuit of the first column is uniquely responsive to a VPI of a particular value for storing the extracted VPI into a bridge memory, and this column has a greater number of policing circuits than any of the other columns of the array. In each column of the array, at least one of the policing circuits includes a cell counter for incrementing a cell count value in response to the VPI of every incoming cell and decrementing the cell count in response to a VPI read out of the bridge memory of the policing circuit. The cell count value is compared with the threshold value and a cell is discarded from the cell buffer when the cell count value exceeds the threshold value.
摘要翻译：在ATM网络的监管安排中，每个传入小区被存储在小区缓冲器中，并且包含在小区中的虚拟路径标识符（VPI）被提取并转换成一组阈值中的对应的一个。矩阵阵列的监控电路逐列连接，以便根据读/写控制电路传输VPI。第一列的每个监管电路唯一地响应用于将提取的VPI存储到桥接存储器中的特定值的VPI，并且该列具有比阵列的任何其他列中更多数量的监管电路。在阵列的每一列中，至少一个监管电路包括一个单元计数器，用于响应于每个输入单元的VPI递增单元计数值，并响应于桥接器读出的VPI而递减单元计数监管电路。将小区计数值与阈值进行比较，并且当小区计数值超过阈值时，从小区缓冲器中丢弃小区。

2. 发明授权

US5394408A Policing control apparatus 失效
标题翻译：监管控制装置
公开(公告)号：US5394408A
公开(公告)日：1995-02-28
申请号：US15343
申请日：1993-02-08
申请人： Motoo Nishihara , Takatoshi Kurano , Naoaki Yamanaka , Youichi Sato
发明人： Motoo Nishihara , Takatoshi Kurano , Naoaki Yamanaka , Youichi Sato
IPC分类号： H04L12/54 , H04L12/70 , H04Q11/04 , G06F11/00 , H03M13/00
CPC分类号： H04L12/5602 , H04L2012/5625 , H04L2012/5627 , H04L2012/5636
摘要： A policing control apparatus having a cell input terminal receiving asynchronous transmission communication network cells; a policing circuit coupled to the input terminal for policing transmission of cells according to policing information; a cell output terminal from the policing circuit for outputting policed cells; a count memory in the policing circuit for storing a count value of the cells supplied to the policing circuit and for supplying the count value as the policing information; and a self-diagnosing circuit for monitoring problems and abnormalities of stored contents in the count memory and outputting an alarm upon detection of a problem or abnormality.
摘要翻译：一种监控控制装置，具有接收异步传输通信网络小区的小区输入终端; 耦合到所述输入终端的监管电路，用于根据监管信息来监管小区的传输; 来自用于输出监控单元的监管电路的单元输出端子; 所述监管电路中的计数存储器，用于存储提供给所述监管电路的小区的计数值，并将所述计数值作为所述监管信息提供; 以及用于监视计数存储器中的存储内容的问题和异常的自诊断电路，并且在检测到问题或异常时输出警报。

3. 发明授权

US5414415A Cross-connect apparatus capable of avoiding a superfluous detour route therein 失效
标题翻译：能够避免其中多余的绕行路线的交叉连接装置
公开(公告)号：US5414415A
公开(公告)日：1995-05-09
申请号：US15651
申请日：1993-02-09
申请人： Hiromi Ueda , Ikuo Tokizawa , Kazuo Iguchi , Haruo Yamashita , Takatoshi Kurano , Motoo Nishihara
发明人： Hiromi Ueda , Ikuo Tokizawa , Kazuo Iguchi , Haruo Yamashita , Takatoshi Kurano , Motoo Nishihara
IPC分类号： H04Q3/52 , H04L12/931 , H04L12/933 , H04Q11/04 , H01H67/00
CPC分类号： H04L49/104 , H04L49/15 , H04L2012/561
摘要： In a cross-connect apparatus for use in selectively connecting a plurality of input transmission paths to a plurality of output transmission paths, each of the input and the output transmission paths is divided into first through m-th groups each of which is composed of first through n-th transmission paths, first through m-th elementary switch modules are located between the input and the output transmission paths, n in number, of the first through the m-th groups and are connected to a connection switch module through first to m-th input internal path groups each of which is composed of n internal paths and which are extended into first through m-th switch units each of which has input terminals, n(m-1) in number, and output terminals, n in number, where n and m are natural numbers. An i-th one of the switch units in the connection switch module is connected to the input path groups, (m-1) in number, except an i-th internal path group, where i is a natural number between unity and m, both inclusive. The output terminals of the i-th switch unit is connected to an i-th one of the elementary switch modules through an i-th one of output internal paths. This structure serves to avoid an unnecessary detour route in the cross-connect apparatus.
摘要翻译：在用于选择性地将多个输入传输路径连接到多个输出传输路径的交叉连接装置中，输入和输出传输路径中的每一个被分成第一至第m组，每个组由第一组通过第n个传输路径，第一到第m个基本交换模块位于第一至第m组的输入和输出传输路径之间，n个数量上，并且首先通过连接交换模块连接到第m个输入内部路径组，每个由n个内部路径组成，并且被扩展到第一至第m个开关单元，每个开关单元具有输入端子，数量为n（m-1），输出端子n 数，其中n和m是自然数。连接开关模块中的第i个开关单元连接到输入路径组（m-1），除了第i个内部路径组，其中i是单位和m之间的自然数，包括在内第i个开关单元的输出端通过第i个输出内部通路连接到基本开关模块的第i个。该结构用于避免交叉连接装置中的不必要的迂回路径。

4. 发明授权

US5450440A Monitor system for digital communication apparatus 失效
标题翻译：数字通信设备监控系统
公开(公告)号：US5450440A
公开(公告)日：1995-09-12
申请号：US964135
申请日：1992-10-22
申请人： Motoo Nishihara , Takatoshi Kurano , Kenji Akutsu , Hiromi Ueda
发明人： Motoo Nishihara , Takatoshi Kurano , Kenji Akutsu , Hiromi Ueda
IPC分类号： H04L29/14 , H04L1/24 , H04M3/24 , H04B3/46 , H04B17/00 , H04Q1/20
CPC分类号： H04L1/24 , H04M3/244
摘要： In a monitor system in a digital communication apparatus including communication processing blocks on transmission paths of digital data, test data inserting units and data monitor units are arranged such that a monitor interval for the monitor operation in a block overlaps with a monitor period for the monitor operation between adjacent blocks in each processing block. As a result, there is no unmonitored interval in each processing block, thereby achieving a complete monitor operation.
摘要翻译：在包括数字数据的传输路径上的通信处理块的数字通信装置的监视器系统中，布置测试数据插入单元和数据监视单元，使得块中的监视操作的监视间隔与监视器的监视周期重叠在每个处理块中的相邻块之间的操作。结果，在每个处理块中没有不间断的间隔，从而实现完整的监视操作。

5. 发明授权

US5323399A ATM cell multiplexing device capable of reducing an accessing speed to a FIFO memory thereof 失效
标题翻译： ATM信元多路复用装置能够降低对其FIFO存储器的访问速度
公开(公告)号：US5323399A
公开(公告)日：1994-06-21
申请号：US859009
申请日：1992-03-30
申请人： Takatoshi Kurano
发明人： Takatoshi Kurano
IPC分类号： H04L12/54 , H04L12/70 , H04L12/933 , H04J3/04
CPC分类号： H04L12/5601 , H04L49/107 , H04L2012/5672 , H04L2012/5681
摘要： On time division multiplexing first through N-th input signals, each having a bit rate V to represent successive ATM cells, a multiplexing section (12, 13') multiplexes the first through the N-th input signals and a dummy input signal into a time division multiplexed signal having another bit rate V.times.(N+1) and comprising first through N-th multiplexed cells and a dummy multiplexed cell. The first through the N-th and the dummy multiplexed cells are derived from the first through the N-th and the dummy input signals, respectively. A controller (16') successively writes valid cells of the first through the N-th multiplexed cells in an FIFO memory (15) as written cells at a writing rate equal to the bit rate V.times.(N+1) for a writing time interval defined by the first through the N-th multiplexed cells and reads the written cells from the FIFO memory in a first-in first-out order as a read-out signal at a reading rate equal to the bit rate V.times.(N+1) for a reading time interval defined by the dummy multiplexed cell. A converter (17) converts the read-out signal into a multiplexed output signal having the bit rate V.
摘要翻译：在第一至第N输入信号上进行时分复用，每个具有表示连续ATM信元的比特率V，复用部分（12,13'）将第一至第N输入信号和虚拟输入信号复用为具有另一比特率Vx（N + 1）并且包括第一至第N多路复用单元和虚拟多路复用单元的时分复用信号。从第一到第N和虚拟多路复用单元分别从第一到第N和虚拟输入信号导出。控制器（16'）以等于写入时间间隔的比特率Vx（N + 1）的写入速率将先到先然的第N个复用单元的有效单元顺序地写入FIFO存储器（15）由第一至第N多路复用单元定义，并以等于比特率Vx（N + 1）的读出速率，以先进先出顺序读出来自FIFO存储器的写入单元作为读出信号，对于由虚拟多路复用单元定义的读取时间间隔。 A转换器（17）将读出的信号转换为具有比特率V的多路复用输出信号。

6. 发明授权

US5249178A Routing system capable of effectively processing routing information 失效
标题翻译：能够有效处理路由信息的路由系统
公开(公告)号：US5249178A
公开(公告)日：1993-09-28
申请号：US736200
申请日：1991-07-26
申请人： Takatoshi Kurano , Takayuki Kobayashi , Hiroshi Yamashita
发明人： Takatoshi Kurano , Takayuki Kobayashi , Hiroshi Yamashita
IPC分类号： H04L12/70 , H04L12/931 , H04L12/935 , H04L12/947
CPC分类号： H04L49/3009 , H04L49/256 , H04L49/3081 , H04L49/505 , H04L2012/5672 , H04L49/25 , H04L49/30 , H04L49/501
摘要： In a routing system having a plurality of external input ports and a plurality of external output ports, a switch network having a plurality of internal input ports and a plurality of internal output ports, an input section between the external input ports and the internal input ports, an output section between the internal output ports and the external output ports, and a control section connected to the switch network and the input section, an input port number which may be assigned to each of the external input ports is arranged in a routing information field of a transmission path signal by an input port number setter included in the input section. The input port number is memorized in a discarded cell memory of the control section together with an internal output port number which is assigned to the internal output ports and which is derived from a routing table along with a header. On occurrence of a discarded cell, the cause of discard can be analyzed by the use of the input port number and the header. When a plurality of external input cells are multiplexed into a multiplexed input cell sequence, the input port number may be replaced by the internal output port number in the control section to effectively utilize the routing information field.

7. 发明授权

US5359600A High throughput supervisory system for ATM switching systems transporting STM-N signals 失效
标题翻译：用于传输STM-N信号的ATM交换系统的高吞吐量监控系统
公开(公告)号：US5359600A
公开(公告)日：1994-10-25
申请号：US017744
申请日：1993-02-16
申请人： Hiromi Ueda , Kenji Akutsu , Ryuichi Ikematsu , Takatoshi Kurano , Yoshihiro Ashi , Yukio Nakano , Takafumi Chujo , Shigeo Amemiya
发明人： Hiromi Ueda , Kenji Akutsu , Ryuichi Ikematsu , Takatoshi Kurano , Yoshihiro Ashi , Yukio Nakano , Takafumi Chujo , Shigeo Amemiya
IPC分类号： H04L12/70 , H04Q11/04 , H04L12/56
CPC分类号： H04L49/30 , H04L49/3081 , H04L49/555 , H04Q11/0478 , H04L2012/5625 , H04L2012/5628 , H04L2012/5652 , H04L49/254
摘要： In an ATM switching network, ATM (asynchronous transfer mode) self-routing switches are interconnected by facilities carrying STM-N (synchronous transport modules level N) signals. At each inlet of an ATM self-routing switch, an STM overhead is removed from each frame of an incoming STM-N signal to create a vacant interval and the frame is converted according to ATM cell format into a series of data ATM cells, and an idle ATM cell is derived from the vacant interval. A supervisory bit sequence is inserted to the payload field of the idle ATM cell to produce a supervisory ATM cell, and the data and supervisory ATM cells are sent into the ATM switch. At each outlet of the switch, the bit sequence of the supervisory ATM cell is checked to evaluate the quality of the ATM switch and a series of data ATM cells is then converted into an STM-N signal according to STM-N frame format.
摘要翻译：在ATM交换网络中，ATM（异步传输模式）自路由交换机通过携带STM-N（同步传输模块级N）信号的设施互连。在ATM自路由交换机的每个入口处，从进入的STM-N信号的每个帧中移除STM开销，以创建空闲间隔，并且该帧根据ATM信元格式被转换成一系列数据ATM信元，并且从空闲间隔导出空闲ATM信元。监控比特序列被插入到空闲ATM信元的有效载荷字段，以产生一个监控的ATM信元，数据和监控的ATM信元被发送到ATM交换机。在交换机的每个出口处，检查监控ATM信元的比特序列，以评估ATM交换机的质量，然后根据STM-N帧格式将一系列数据ATM信元转换成STM-N信号。

8. 发明授权

US5619510A Output buffer type asynchronous transfer mode switch and detecting error boards thereof 失效
标题翻译：输出缓冲器型异步传输模式切换和检测错误板
公开(公告)号：US5619510A
公开(公告)日：1997-04-08
申请号：US490891
申请日：1995-06-15
申请人： Takatoshi Kurano
发明人： Takatoshi Kurano
IPC分类号： H04Q3/00 , H04J3/06 , H04J3/14 , H04L12/70 , H04L12/931 , H04L12/945 , H04Q3/52 , H04L12/26
CPC分类号： H04L12/5601 , H04J3/0697 , H04L49/107 , H04L49/255 , H04L49/3081 , H04L2012/5674 , H04L2012/5681
摘要： A buffer control circuit is arranged for each of a master board and a slave board having FIFO buffers corresponding to each output port. Each of the buffer control circuits is arranged on the boards in a bit-slice structure. The buffer control circuit on the side of the master board transmits a synchronizing control signal to the corresponding buffer control circuit on the side of the slave boards. The buffer control circuit resets the corresponding FIFO buffer to synchronize the boards, when routing control signals indicate empty cell, or output ports to which the cells are not addressed and an empty FIFO buffer 14 exists. A monitoring trigger is periodically input to the buffer control circuit 21 at predetermined intervals, and the number of cells in the FIFO buffer on each of the boards are compared for each destinations at the time of inputting the monitoring trigger. Synchronizing each boards is carried out by resetting all of the FIFO buffers on the boards for the destination for which the number of the cells does not coincide. An output buffer type ATM switch of the present invention is capable of synchronizing-each of the boards consisting of the switch without a monitoring cell.
摘要翻译：为每个具有对应于每个输出端口的FIFO缓冲器的主板和从属板设置缓冲器控制电路。每个缓冲器控制电路以位片结构布置在电路板上。主板一侧的缓冲器控制电路将同步控制信号发送到从板侧的相应的缓冲器控制电路。当路由控制信号指示空单元或单元未被寻址的输出端口和空FIFO缓冲器14存在时，缓冲器控制电路复位对应的FIFO缓冲器以使板同步。监视触发器以预定的间隔周期性地输入到缓冲器控制电路21，并且在输入监视触发时对每个目的地的每个目的地上的FIFO缓冲器中的单元的数量进行比较。通过重置每个单元格不一致的目的地的板上的所有FIFO缓冲区来实现每个单板的同步。本发明的输出缓冲器型ATM交换机能够在没有监视单元的情况下同步由开关构成的各个板。

9. 发明授权

US5671213A Duplicated arrangement for ATM switching system 失效
标题翻译： ATM交换系统的重复安排
公开(公告)号：US5671213A
公开(公告)日：1997-09-23
申请号：US552533
申请日：1995-11-06
申请人： Takatoshi Kurano
发明人： Takatoshi Kurano
IPC分类号： H04Q3/00 , H04L12/70 , H04Q3/52 , H04Q11/04 , H04L12/56
CPC分类号： H04L49/103 , H04L49/3027 , H04L49/3081 , H04L49/552
摘要： In a duplicated arrangement for an ATM switching system, first and second store-and-forward buffers are provided for storing and forwarding an ATM cell stream and first and second counters are responsive to a timing signal for producing a first cell count and a second cell count representative of counts of cells stored in the first and second store-and-forward buffers, respectively. A detector is provided for detecting a difference between the first and second cell counts. A buffer controller controls the second store-and-forward buffer in accordance with the difference so that the count of cells in the second buffer approaches the count of cells in the first buffer. A switching circuit normally couples the ATM cell stream forwarded from the first buffer to an output port of the ATM switching system and couples the ATM cell stream forwarded from the second buffer, instead of from the first buffer, to the output port in response to a switching command signal.
摘要翻译：在用于ATM交换系统的重复布置中，提供第一和第二存储转发缓冲器用于存储和转发ATM信元流，并且第一和第二计数器响应于用于产生第一信元计数的定时信号和第二信元分别表示存储在第一和第二存储和转发缓冲器中的单元的计数的计数。提供了一种用于检测第一和第二细胞计数之间的差异的检测器。缓冲器控制器根据差异控制第二存储和转发缓冲器，使得第二缓冲器中的单元的计数接近第一缓冲器中的单元计数。切换电路通常将从第一缓冲器转发的ATM信元流耦合到ATM交换系统的输出端口，并且将来自第二缓冲器而不是从第一缓冲器转发的ATM信元流耦合到输出端口，以响应于切换命令信号。

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