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    • 1. 发明授权
    • Power semiconductor device including a bootstrap compensation circuit
    • 功率半导体器件,包括自举补偿电路
    • US08724357B2
    • 2014-05-13
    • US13010178
    • 2011-01-20
    • Motoki ImanishiKenji SakaiYoshikazu Tanaka
    • Motoki ImanishiKenji SakaiYoshikazu Tanaka
    • H02M7/5387H02M1/084
    • H02M1/08H03K17/063
    • A power semiconductor device comprises: high side and low side switching elements; high side and low side drive circuits; a bootstrap capacitor supplying a drive voltage to the high side drive circuit and having a first terminal connected to a connection point between the high side switching element and the low side switching element and a second terminal connected to a power supply terminal of the high side drive circuit; a bootstrap diode having an anode connected to a power supply and a cathode connected to the second terminal and supplying a current from the power supply to the second terminal; a floating power supply; and a bootstrap compensation circuit supplying a current from the floating power supply to the second terminal, when the high side drive circuit turns ON the high side switching element and the low side drive circuit turns OFF the low side switching element.
    • 功率半导体器件包括:高侧和低侧开关元件; 高侧和低侧驱动电路; 向高侧驱动电路供给驱动电压并具有与高侧开关元件和低侧开关元件之间的连接点连接的第一端子的自举电容器和连接到高侧驱动器的电源端子的第二端子 电路 引导二极管,其具有连接到电源的阳极和连接到第二端子的阴极,并且将电流从电源提供给第二端子; 浮动电源; 以及当所述高侧驱动电路导通所述高侧开关元件并且所述低侧驱动电路使所述低侧开关元件断开时,从所述浮动电源向所述第二端子供给电流的自举补偿电路。
    • 2. 发明申请
    • SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DEVICE
    • 半导体电路和半导体器件
    • US20120154007A1
    • 2012-06-21
    • US13228903
    • 2011-09-09
    • Motoki IMANISHIKenji SakaiYoshikazu TanakaKyouko Oyama
    • Motoki IMANISHIKenji SakaiYoshikazu TanakaKyouko Oyama
    • H03K3/356
    • H03K17/162H01L2924/0002H01L2924/00
    • A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor.
    • 本发明的半导体电路包括:用于响应于ON驱动信号对接通驱动电荷进行充电的电容器;响应于OFF驱动信号而对驱动电荷进行充电的电容器;产生第一触发信号的信号产生电路 响应于ON驱动信号,产生响应于OFF驱动信号产生第二触发信号的信号发生电路,用于响应于第二触发信号对ON驱动电荷进行放电的放电电路,以及用于放电的放电电路 OFF驱动电荷响应于第一触发信号。 利用这种结构,可以提供一种具有通用故障防止功能的半导体电路和半导体器件,通过该功能可以防止由于dV / dt引起的故障,而不受任何外部因素的影响。
    • 3. 发明申请
    • POWER SEMICONDUCTOR DEVICE
    • 功率半导体器件
    • US20110260707A1
    • 2011-10-27
    • US13010178
    • 2011-01-20
    • Motoki IMANISHIKenji SakaiYoshikazu Tanaka
    • Motoki IMANISHIKenji SakaiYoshikazu Tanaka
    • G05F3/02
    • H02M1/08H03K17/063
    • A power semiconductor device comprises: high side and low side switching elements; high side and low side drive circuits; a bootstrap capacitor supplying a drive voltage to the high side drive circuit and having a first terminal connected to a connection point between the high side switching element and the low side switching element and a second terminal connected to a power supply terminal of the high side drive circuit; a bootstrap diode having an anode connected to a power supply and a cathode connected to the second terminal and supplying a current from the power supply to the second terminal; a floating power supply; and a bootstrap compensation circuit supplying a current from the floating power supply to the second terminal, when the high side drive circuit turns ON the high side switching element and the low side drive circuit turns OFF the low side switching element.
    • 功率半导体器件包括:高侧和低侧开关元件; 高侧和低侧驱动电路; 向高侧驱动电路供给驱动电压并具有与高侧开关元件和低侧开关元件之间的连接点连接的第一端子的自举电容器和连接到高侧驱动器的电源端子的第二端子 电路 引导二极管,其具有连接到电源的阳极和连接到第二端子的阴极,并且将电流从电源提供给第二端子; 浮动电源; 以及当所述高侧驱动电路导通所述高侧开关元件并且所述低侧驱动电路使所述低侧开关元件断开时,从所述浮动电源向所述第二端子供给电流的自举补偿电路。
    • 4. 发明授权
    • Semiconductor circuit and semiconductor device
    • 半导体电路和半导体器件
    • US08803561B2
    • 2014-08-12
    • US13228903
    • 2011-09-09
    • Motoki ImanishiKenji SakaiYoshikazu TanakaKyouko Oyama
    • Motoki ImanishiKenji SakaiYoshikazu TanakaKyouko Oyama
    • H03K3/00
    • H03K17/162H01L2924/0002H01L2924/00
    • A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor.
    • 本发明的半导体电路包括:用于响应于ON驱动信号对接通驱动电荷进行充电的电容器;响应于OFF驱动信号而对驱动电荷进行充电的电容器;产生第一触发信号的信号产生电路 响应于ON驱动信号,产生响应于OFF驱动信号产生第二触发信号的信号发生电路,用于响应于第二触发信号对ON驱动电荷进行放电的放电电路,以及用于放电的放电电路 OFF驱动电荷响应于第一触发信号。 利用这种结构,可以提供一种具有通用故障防止功能的半导体电路和半导体器件,通过该功能可以防止由于dV / dt引起的故障,而不受任何外部因素的影响。
    • 5. 发明授权
    • Status scheme signal processing circuit
    • 状态方案信号处理电路
    • US06856166B2
    • 2005-02-15
    • US10388497
    • 2003-03-17
    • Kenji SakaiYoshikazu Tanaka
    • Kenji SakaiYoshikazu Tanaka
    • H03K5/1532G06F7/38H03K5/04H03K5/135H03K5/153H03K19/00H03K19/173
    • H03K5/135H03K5/04H03K5/153
    • In a status scheme signal processing circuit which obtains a desired output signal on the basis of an OR signal between a pulse output from a one-shot pulse circuit at an edge of an input signal and a status signal, since the input signal and the status signal are not synchronized with each other, the output timing of the output signal changes depending on the timing of the input signal. Therefore, in the present invention, a mask signal generator which outputs a mask signal having a predetermined bandwidth T1 in response to a signal leading edge and a signal trailing edge of the input signal, and said desired output signal is masked (disabled) with the mask signal, so that an output signal is always obtained a predetermined period (T1) after the input timing of the input signal.
    • 在状态方案信号处理电路中,根据在输入信号的边缘的单触发脉冲电路输出的脉冲与状态信号之间的或信号获得期望的输出信号,由于输入信号和状态 信号彼此不同步,输出信号的输出定时根据输入信号的定时而改变。 因此,在本发明中,掩蔽信号发生器响应于输入信号的信号前沿和信号后沿输出具有预定带宽T1的屏蔽信号和所述期望输出信号被屏蔽(禁用) 掩模信号,使得在输入信号的输入定时之后总是获得预定周期(T1)的输出信号。
    • 6. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20080278215A1
    • 2008-11-13
    • US11860123
    • 2007-09-24
    • Kenji SakaiYoshikazu Tanaka
    • Kenji SakaiYoshikazu Tanaka
    • H03K17/28
    • H02M1/08H03K17/162H03K17/284H03K17/6871H03K19/018507
    • A semiconductor device according to the present invention is a semiconductor device for driving and controlling a power device in the high-potential side of two power devices connected in series between a main power source potential of a high potential and a main power source potential of a low potential, and is equipped with a pulse generating circuit for generating first and second pulse signals corresponding to the level transition to first and second states of input signals having a first state showing the conduction of the power device in the high-potential side and a second state showing the non-conduction of the power device in the high-potential side, respectively; a level shift circuit for obtaining first and second level-shifted pulse signals by level-shifting the first and second pulse signals to the high-potential side; an SR-type flip-flop circuit inputting the first level-shifted pulse signals from set input terminal and the second level-shifted pulse signals from reset input terminal; and a delay circuit for delaying the output of the SR-type flip-flop circuit by at least the pulse width of the first and second pulse signals.
    • 根据本发明的半导体器件是用于驱动和控制在高电位的主电源电位和主电源电位之间串联连接的两个功率器件的高电位侧的功率器件的半导体器件 低电位,并且配备有脉冲发生电路,用于产生对应于具有第一状态的第一和第二状态的第一和第二状态的电平转变的第一和第二脉冲信号,该第一状态具有示出高电位侧的功率器件的导通和 分别表示高电位侧的功率器件的非导通的第二状态; 电平移位电路,用于通过将第一和第二脉冲信号电平移位到高电位侧来获得第一和第二电平移位脉冲信号; 输入来自设定输入端的第一电平移位脉冲信号和来自复位输入端的第二电平移位脉冲信号的SR型触发电路; 以及用于将SR型触发器电路的输出至少延迟第一和第二脉冲信号的脉冲宽度的延迟电路。
    • 7. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07495482B2
    • 2009-02-24
    • US11860123
    • 2007-09-24
    • Kenji SakaiYoshikazu Tanaka
    • Kenji SakaiYoshikazu Tanaka
    • H03B1/00
    • H02M1/08H03K17/162H03K17/284H03K17/6871H03K19/018507
    • A semiconductor device according to the present invention is a semiconductor device for driving and controlling a power device in the high-potential side of two power devices connected in series between a main power source potential of a high potential and a main power source potential of a low potential, and is equipped with a pulse generating circuit for generating first and second pulse signals corresponding to the level transition to first and second states of input signals having a first state showing the conduction of the power device in the high-potential side and a second state showing the non-conduction of the power device in the high-potential side, respectively; a level shift circuit for obtaining first and second level-shifted pulse signals by level-shifting the first and second pulse signals to the high-potential side; an SR-type flip-flop circuit inputting the first level-shifted pulse signals from set input terminal and the second level-shifted pulse signals from reset input terminal; and a delay circuit for delaying the output of the SR-type flip-flop circuit by at least the pulse width of the first and second pulse signals.
    • 根据本发明的半导体器件是用于驱动和控制在高电位的主电源电位和主电源电位之间串联连接的两个功率器件的高电位侧的功率器件的半导体器件 低电位,并且配备有脉冲发生电路,用于产生对应于具有第一状态的第一和第二状态的第一和第二状态的电平转变的第一和第二脉冲信号,该第一状态具有示出高电位侧的功率器件的导通和 分别表示高电位侧的功率器件的非导通的第二状态; 电平移位电路,用于通过将第一和第二脉冲信号电平移位到高电位侧来获得第一和第二电平移位脉冲信号; 输入来自设定输入端的第一电平移位脉冲信号和来自复位输入端的第二电平移位脉冲信号的SR型触发电路; 以及用于将SR型触发器电路的输出至少延迟第一和第二脉冲信号的脉冲宽度的延迟电路。