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1. 发明申请

US20110032993A1 IMAGE DECODING DEVICE, IMAGE DECODING METHOD, INTEGRATED CIRCUIT, AND RECEIVING DEVICE 审中-公开
标题翻译：图像解码装置，图像解码方法，集成电路和接收装置
公开(公告)号：US20110032993A1
公开(公告)日：2011-02-10
申请号：US12934134
申请日：2009-03-16
申请人： Motokazu Ozawa , Takaaki Imanaka , Mitsunori Houki
发明人： Motokazu Ozawa , Takaaki Imanaka , Mitsunori Houki
IPC分类号： H04N7/26
CPC分类号： H04N19/523 , H04N19/182 , H04N19/433 , H04N19/44
摘要： An image memory access control unit (502) judges whether or not an additional pixel required for motion compensation is necessary, the additional pixel not being included in a plurality of pixels forming an image shown by a reference block. When the additional pixel is judged to be necessary, a yet-to-be-obtained-pixel interpolating unit (503) generates at least one additional pixel, and generates a reference image to be used for motion compensation using the generated at least one additional pixel and at least a part of the image shown by the reference block. When the additional pixel is judged to be unnecessary, the yet-to-be-obtained-pixel interpolating unit (503) outputs at least a part of the image shown by the reference block as the reference image.
摘要翻译：图像存储器访问控制单元（502）判断是否需要运动补偿所需的附加像素，附加像素不包括在形成由参考块所示的图像的多个像素中。当附加像素被判断为必需时，尚未被获得的像素内插单元（503）生成至少一个附加像素，并且使用所生成的至少一个附加的像素生成用于运动补偿的参考图像像素和参考块所示的图像的至少一部分。当附加像素被判定为不需要时，尚未获得的像素内插单元（503）输出由参考块所示的图像的至少一部分作为参考图像。

2. 发明申请

US20090196356A1 MULTI-STREAM DECODER APPARATUS 审中-公开
标题翻译：多流道解码器设备
公开(公告)号：US20090196356A1
公开(公告)日：2009-08-06
申请号：US12067001
申请日：2006-05-23
申请人： Mitsunori Houki
发明人： Mitsunori Houki
IPC分类号： H04N7/26 , H04L27/00
CPC分类号： H04N21/434 , H04N21/23424 , H04N21/42607 , H04N21/44016
摘要： A time management section (102) and a bitstream switching control section (103) are provided in a decoder control device (100), and at the end of a predetermined unit of decoding process, a decoder (110) notifies the switching control section (103) of the completion of the decoding process. The time management section (102) sets the limit time that is allowed for decoding each bitstream within the prescribed time based on the decoder capacity, the information on the number of bitstreams to be decoded, the image size information and the frame rate extracted from the bitstream. If the limit time is reached, the switching control section (103) is instructed to switch bitstreams from one to another. The switching control section (103) switches bitstreams from one to another, by receiving the switching instruction from the time management section (102) and the completion notification from the decoder (110) notifying the completion of the predetermined unit of decoding process.
摘要翻译：在解码器控制装置（100）中设置有时间管理部（102）和比特流切换控制部（103），在解码处理的规定单位结束时，解码器（110）通知切换控制部 103）完成解码过程。时间管理部（102）基于解码器容量设定在规定时间内对每个比特流进行解码所允许的限制时间，关于要解码的比特流的数量的信息，图像尺寸信息和从比特流。如果达到限制时间，则指示切换控制部分（103）将比特流从一个切换到另一个。切换控制部（103）通过从时间管理部（102）接收到切换指示和来自解码器（110）的通知完成解码处理的预定单元的完成通知，将比特流从一个切换到另一个。

3. 发明授权

US08135909B2 System for starting a preload of a second program while a first program is executing 有权
标题翻译：用于在第一程序执行时启动第二程序的预加载的系统
公开(公告)号：US08135909B2
公开(公告)日：2012-03-13
申请号：US10946009
申请日：2004-09-22
申请人： Mitsunori Houki
发明人： Mitsunori Houki
IPC分类号： G06F12/00
CPC分类号： G06F9/4812 , G06F9/485 , G06F12/0862
摘要： A program is divided into unified units, and necessary instructions are downloaded for each of the unified units in advance from a main memory to a cache memory before a processor executes the instructions, to thereby reduce occurrence of a miss hit. If a miss hit occurs, an application program is switched to another one to conceal the miss hit penalty, to thereby enhance the serviceability of programs and thus achieve real time processing while swapping instructions.
摘要翻译：将程序分为统一单元，并且在处理器执行指令之前，从主存储器到高速缓冲存储器，预先从每个统一单元下载必要的指令，从而减少错误命中的发生。如果发生错误命中，则将应用程序切换到另一个应用程序以隐藏错误命中，从而增强程序的可服务性，从而在交换指令的同时实现实时处理。

4. 发明申请

US20050066132A1 Information processing control system 有权
标题翻译：信息处理控制系统
公开(公告)号：US20050066132A1
公开(公告)日：2005-03-24
申请号：US10946009
申请日：2004-09-22
申请人： Mitsunori Houki
发明人： Mitsunori Houki
IPC分类号： G06F9/38 , G06F9/46 , G06F9/48 , G06F9/50 , G06F12/08 , G06F12/00
CPC分类号： G06F9/4812 , G06F9/485 , G06F12/0862
摘要： A program is divided into unified units, and necessary instructions are downloaded for each of the unified units in advance from a main memory to a cache memory before a processor executes the instructions, to thereby reduce occurrence of a miss hit. If a miss hit occurs, an application program is switched to another one to conceal the miss hit penalty, to thereby enhance the serviceability of programs and thus achieve real time processing while swapping instructions.
摘要翻译：将程序分为统一单元，并且在处理器执行指令之前，从主存储器到高速缓冲存储器，预先从每个统一单元下载必要的指令，从而减少错误命中的发生。如果发生错误命中，则将应用程序切换到另一个应用程序以隐藏错误命中，从而增强程序的可服务性，从而在交换指令的同时实现实时处理。

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