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1. 发明申请

US20070297893A1 Fan speed change control 审中-公开
标题翻译：风机变速控制
公开(公告)号：US20070297893A1
公开(公告)日：2007-12-27
申请号：US11475223
申请日：2006-06-27
申请人： Moshe Alon , Nir Tasher , Lior Albaz
发明人： Moshe Alon , Nir Tasher , Lior Albaz
IPC分类号： F04D15/00 , H05K7/20
CPC分类号： F04D27/004 , F04D25/166 , H05K7/20209
摘要： Methods and systems for controlling the speed of a fan for an electronic system. In some embodiments of the invention, temperatures are associated with changes in the value of a variable relating to fan speed. In one of these embodiments, there is a range of temperatures where the fan speed is fixed. In one embodiment of the invention, where there is a plurality of temperature readings associated with a fan, the temperature reading which would result in the highest fan speed is operative. In one embodiment of the invention, the fan speed control is capable of automatic self-adjustment.
摘要翻译：用于控制电子系统风扇速度的方法和系统。在本发明的一些实施例中，温度与与风扇速度相关的变量的值的变化相关联。在这些实施例中的一个中，存在风扇速度固定的温度范围。在本发明的一个实施例中，当存在与风扇相关联的多个温度读数时，将导致最高风扇速度的温度读数是可操作的。在本发明的一个实施例中，风扇速度控制能够进行自动自调节。

2. 发明授权

US08688944B2 Memory sharing between embedded controller and central processing unit chipset 有权
标题翻译：嵌入式控制器与中央处理器芯片组之间的内存共享
公开(公告)号：US08688944B2
公开(公告)日：2014-04-01
申请号：US13236673
申请日：2011-09-20
申请人： Moshe Alon , Michal Schramm , Nir Tasher
发明人： Moshe Alon , Michal Schramm , Nir Tasher
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F13/1663 , Y02D10/14
摘要： An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.
摘要翻译：嵌入式控制器包括微控制器核心和存储器控制电路。存储器控制电路经配置以通过第一串行外设接口（SPI）与第一串行外设接口（SPI）进行通信，对于该第一串行外设接口（SPI），不支持总线仲裁，以第一时钟速率通过第二SPI与存储器进行通信以第二固定时钟速率，通过第一和第二SPI来中继CPU芯片组和存储器之间的存储器事务，以识别在第二SPI上没有存储器事务中继的时间间隔，并且从存储器检索用于操作的信息在确定的时间间隔内的微控制器内核。

3. 发明申请

US20120239848A1 MITIGATION OF EMBEDDED CONTROLLER STARVATION IN REAL-TIME SHARED SPI FLASH ARCHITECTURE 有权
标题翻译：嵌入式控制器启动实时共享SPI闪存架构
公开(公告)号：US20120239848A1
公开(公告)日：2012-09-20
申请号：US13360746
申请日：2012-01-29
申请人： Moshe Alon , Ilia Stolov , Erez Naory , Nir Tasher , Yuval Kirschner , Michal Schramm
发明人： Moshe Alon , Ilia Stolov , Erez Naory , Nir Tasher , Yuval Kirschner , Michal Schramm
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , Y02D10/14
摘要： An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.
摘要翻译：嵌入式控制器包括微控制器核心，不支持总线仲裁的第一总线接口，第二总线接口和存储器控制电路。第一总线接口被配置为从中央处理器（CPU）芯片组接收和发送存储器事务。第二总线接口被配置为与存储器通信并将CPU芯片组的存储器事务传送到存储器和从存储器传送。存储器控制电路被配置为评估由于经由第一和第二总线接口在CPU芯片组和存储器之间传送的存储器事务而识别微控制器核心经由第二总线接口访问存储器的不足的饥饿状况，以及在满足饥饿条件时调用预定义的纠正措施。

4. 发明授权

US08543755B2 Mitigation of embedded controller starvation in real-time shared SPI flash architecture 有权
标题翻译：实时共享SPI闪存架构中的嵌入式控制器饥饿的缓解
公开(公告)号：US08543755B2
公开(公告)日：2013-09-24
申请号：US13360746
申请日：2012-01-29
申请人： Moshe Alon , Ilia Stolov , Erez Naory , Nir Tasher , Yuval Kirschner , Michal Schramm
发明人： Moshe Alon , Ilia Stolov , Erez Naory , Nir Tasher , Yuval Kirschner , Michal Schramm
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , Y02D10/14
摘要： An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.
摘要翻译：嵌入式控制器包括微控制器核心，不支持总线仲裁的第一总线接口，第二总线接口和存储器控制电路。第一总线接口被配置为从中央处理器（CPU）芯片组接收和发送存储器事务。第二总线接口被配置为与存储器通信并将CPU芯片组的存储器事务传送到存储器和从存储器传送。存储器控制电路被配置为评估由于经由第一和第二总线接口在CPU芯片组和存储器之间传送的存储器事务而识别微控制器核心经由第二总线接口访问存储器的不足的饥饿状况，以及在满足饥饿条件时调用预定义的纠正措施。

5. 发明申请

US20130073810A1 Memory Sharing Between Embedded Controller and Central Processing Unit Chipset 有权
标题翻译：嵌入式控制器与中央处理单元芯片组之间的内存共享
公开(公告)号：US20130073810A1
公开(公告)日：2013-03-21
申请号：US13236673
申请日：2011-09-20
申请人： Moshe Alon , Michal Schramm , Nir Tasher
发明人： Moshe Alon , Michal Schramm , Nir Tasher
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F13/1663 , Y02D10/14
摘要： An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.
摘要翻译：嵌入式控制器包括微控制器核心和存储器控制电路。存储器控制电路经配置以通过第一串行外设接口（SPI）与第一串行外设接口（SPI）进行通信，对于该第一串行外设接口（SPI），不支持总线仲裁，以第一时钟速率通过第二SPI与存储器进行通信以第二固定时钟速率，通过第一和第二SPI来中继CPU芯片组和存储器之间的存储器事务，以识别在第二SPI上没有存储器事务中继的时间间隔，并且从存储器检索用于操作的信息在确定的时间间隔内的微控制器内核。

6. 发明授权

US08169419B2 Power efficient capacitive detection 有权
标题翻译：高效电容检测
公开(公告)号：US08169419B2
公开(公告)日：2012-05-01
申请号：US12853570
申请日：2010-08-10
申请人： Nir Tasher , Vladimir Abramov , Yehezkel Friedman , Einat Nosovitsky , Mark Lukoyanichev
发明人： Nir Tasher , Vladimir Abramov , Yehezkel Friedman , Einat Nosovitsky , Mark Lukoyanichev
IPC分类号： G06F3/045
CPC分类号： G01D5/2405 , G06F3/0416 , G06F3/044
摘要： Capacitive detection systems, modules, and methods. In one embodiment, a power saving mode is implemented when deemed appropriate, based on an analysis of previous detection or non-detection of the presence and/or position of an object near a capacitive sensing area.
摘要翻译：电容检测系统，模块和方法。在一个实施例中，基于对电容感测区域附近的物体的存在和/或位置的先前检测或不检测的分析，当认为适当时，实现省电模式。

7. 发明授权

US07797115B2 Time interval measurement for capacitive detection 有权
标题翻译：电容检测的时间间隔测量
公开(公告)号：US07797115B2
公开(公告)日：2010-09-14
申请号：US11889435
申请日：2007-08-13
申请人： Nir Tasher , Vladimir Abramov , Yehezkel Friedman
发明人： Nir Tasher , Vladimir Abramov , Yehezkel Friedman
IPC分类号： G01R27/26 , G01R27/00
CPC分类号： G01D5/2405 , G06F3/0416 , G06F3/044
摘要： Capacitive detection systems, modules, and methods. In one embodiment, time interval measurement(s) are generated that are monotonic functions of the capacitance(s) of capacitive sensor(s) in a capacitive sensing area. In one embodiment, the generated time interval measurement(s), or any other monotonic function(s) of capacitance(s) of capacitive sensor(s) in a capacitive sensing area, may be analyzed to detect the presence of an object near the capacitive sensing area and/or to detect the position of an object near the capacitive sensing area.
摘要翻译：电容检测系统，模块和方法。在一个实施例中，产生时间间隔测量，其是电容感测区域中的电容式传感器的电容的单调函数。在一个实施例中，可以分析所产生的时间间隔测量或电容感测区域中的电容式传感器的电容的任何其它单调函数，以检测在电容感测区域和/或检测电容感测区域附近的物体的位置。

8. 发明申请

US20090045823A1 Power efficient capacitive detection 审中-公开
标题翻译：高效电容检测
公开(公告)号：US20090045823A1
公开(公告)日：2009-02-19
申请号：US11889436
申请日：2007-08-13
申请人： Nir Tasher , Vladimir Abramov , Yehezkel Friedman , Einat Nosovitsky , Mark Lukoyanichev
发明人： Nir Tasher , Vladimir Abramov , Yehezkel Friedman , Einat Nosovitsky , Mark Lukoyanichev
IPC分类号： G01R27/26 , G01R15/08
CPC分类号： H03K17/962 , G06F3/044 , H03K2217/960705 , H03K2217/960715
摘要： Capacitive detection systems, modules, and methods. In one embodiment, a power saving mode is implemented when deemed appropriate, based on an analysis of previous detection or non-detection of the presence and/or position of an object near a capacitive sensing area.
摘要翻译：电容检测系统，模块和方法。在一个实施例中，基于对电容感测区域附近的物体的存在和/或位置的先前检测或不检测的分析，当认为适当时，实现省电模式。

9. 发明授权

US08285895B2 Handshake free sharing in a computer architecture 有权
标题翻译：握手在计算机架构中免费共享
公开(公告)号：US08285895B2
公开(公告)日：2012-10-09
申请号：US11834053
申请日：2007-08-06
申请人： Michal Schramm , Nir Tasher
发明人： Michal Schramm , Nir Tasher
IPC分类号： G06F3/00
CPC分类号： G06F13/1663 , G06F13/24
摘要： A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit.
摘要翻译：一种系统装置，包括存储单元，该存储器单元具有根据存储器和访问主机之间的无握手协议的存储器接口，连接到存储器单元的总线以及第一和第二主控器。第一个主机通过总线和存储器接口来操作存储器单元，并且通过中断接口接收到中断请求后执行中断。第二台主机通过总线和存储器接口操作存取存储单元。第二主控器被配置为在访问存储器单元之前将中断请求传送到第一处理器。

10. 发明授权

US07884678B2 Single-pin RC oscillator 有权
标题翻译：单引脚RC振荡器
公开(公告)号：US07884678B2
公开(公告)日：2011-02-08
申请号：US12353307
申请日：2009-01-14
申请人： Nir Tasher , Tamir Golan
发明人： Nir Tasher , Tamir Golan
IPC分类号： H03K3/02
CPC分类号： H03K4/501
摘要： Apparatus includes a single-pin input interface, which is operative to sense a voltage across a capacitor of a Resistor-Capacitor (RC) network in which the capacitor is repetitively charging and discharging so that the voltage oscillates as a function of time. A measurement circuit is coupled to measure time durations in which the capacitor is charging and in which the sensed voltage lies between first and second predefined thresholds. A clock generation circuit is coupled to generate an output clock signal having a frequency, and to adjust the frequency responsively to the measured time durations.
摘要翻译：装置包括单引脚输入接口，其可操作以感测电容器电容器（RC）网络的电容器两端的电压，其中电容器重复充电和放电，使得电压作为时间的函数振荡。耦合测量电路以测量电容器充电的时间长度，并且其中所感测的电压位于第一和第二预定阈值之间。时钟发生电路被耦合以产生具有频率的输出时钟信号，并且响应于测量的持续时间来调整频率。

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