专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2013200889A Hybrid solid-state memory system having volatile memory and non-volatile memory 审中-公开
标题翻译：具有易失性存储器和非易失性存储器的混合固态存储器系统
公开(公告)号：JP2013200889A
公开(公告)日：2013-10-03
申请号：JP2013119104
申请日：2013-06-05
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI
IPC分类号： G06F12/00
CPC分类号： G11C14/0018 , G11C11/005
摘要： PROBLEM TO BE SOLVED: To provide a hybrid solid-state memory system for storing data.SOLUTION: The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. The data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.
摘要翻译：要解决的问题：提供一种用于存储数据的混合固态存储器系统。解决方案：固态存储器系统包括易失性固态存储器，非易失性固态存储器和存储器控制器。此外，提供了一种用于将数据存储在固态存储器系统中的方法。该方法包括以下步骤。存储器控制器接收写命令。响应于写命令，写数据存储在易失性存储器中。响应于数据传输请求，数据从易失性存储器传送到非易失性存储器。

2. 发明专利

JP2013077375A Non-volatile semiconductor memory having multiple external power supply parts 审中-公开
标题翻译：具有多个外部电源部件的非易失性半导体存储器
公开(公告)号：JP2013077375A
公开(公告)日：2013-04-25
申请号：JP2013016683
申请日：2013-01-31
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI , GILLINGHAM PETER
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/30 , G11C5/14 , G11C5/143 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To solve a problem that converting low or lower voltage input to higher voltage to enable memory operations reduces converter efficiency, and increases size and complexity of a charge pump circuit.SOLUTION: A memory device comprises a core memory such as a flash memory for storing data. The memory device comprises a first power input part for receiving first voltage used to supply power to the flash memory. Additionally, the memory device comprises a second power input part for receiving second voltage. The memory device comprises a power management circuit configured to receive the second voltage and draw one or more internal voltage. The power management circuit supplies or conveys the internal voltage to the flash memory. The various internal voltage generated by the power management circuit (e.g., a voltage converter circuit) and supplied to the core memory enable operations such as read, program, and erase with respect to cells in the core memory.
摘要翻译：要解决的问题：为了解决将低电压或低电压输入转换为较高电压以使得存储器操作降低转换器效率并增加电荷泵电路的尺寸和复杂性的问题。解决方案：存储器件包括诸如用于存储数据的闪存的核存储器。存储器件包括用于接收用于向闪存供电的第一电压的第一电源输入部分。另外，存储器件包括用于接收第二电压的第二电源输入部分。存储器件包括被配置为接收第二电压并且抽取一个或多个内部电压的功率管理电路。电源管理电路将内部电压提供或传送到闪存。电源管理电路（例如，电压转换器电路）产生并提供给核心存储器的各种内部电压相对于核心存储器中的单元启用诸如读取，编程和擦除的操作。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2013037712A Daisy chain arrangement of nonvolatile memory 有权
标题翻译：非易失性存储器的DAISY链条布置
公开(公告)号：JP2013037712A
公开(公告)日：2013-02-21
申请号：JP2012210614
申请日：2012-09-25
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI
IPC分类号： G06F13/16 , G06F12/00 , G06F12/06
CPC分类号： G06F13/4247 , G06F13/1684 , G06F13/4234 , G11C16/06 , H01L24/48 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2924/00014 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a memory system that overcomes some of the disadvantages associated with embedded flash memories and other devices.SOLUTION: A flash memory system is implemented in a system-in-package (SIP) enclosure 310, the system comprising a flash memory controller 320 and a plurality of flash memory devices 330a-330n. An SIP applied to a single package or module comprises a number of integrated circuits (chips). The flash memory controller is configured to interface with an external system and a plurality of memory devices within the SIP. The memory devices are configured in daisy chain cascade connection, controlled by the flash memory controller through commands transmitted through the daisy chain cascade.
摘要翻译：要解决的问题：提供克服与嵌入式闪存和其他设备相关的一些缺点的存储器系统。解决方案：闪存系统在系统级封装（SIP）机箱310中实现，该系统包括闪速存储器控制器320和多个闪存器件330a-330n。应用于单个封装或模块的SIP包括多个集成电路（芯片）。闪速存储器控制器被配置为与SIP内的外部系统和多个存储器设备接口。存储器设备配置为菊花链级联，由闪存控制器通过菊花链级联传输的命令控制。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2014017005A Memory system and method with serial and parallel modes 有权
标题翻译：具有串行和并行模式的记忆系统和方法
公开(公告)号：JP2014017005A
公开(公告)日：2014-01-30
申请号：JP2013187117
申请日：2013-09-10
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： PYEON HONG BEOM , OH HAK JUNE , KIM JIN-KI
IPC分类号： G06F12/04 , G06F13/16
CPC分类号： G11C7/1045 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C7/1078 , G11C2207/107
摘要： PROBLEM TO BE SOLVED: To provide methods and systems that allow a method of access to one or more memory banks to be performed using serial access or using parallel access.SOLUTION: In a serial mode, each link operates as an independent serial link. In contrast, during a parallel mode, the links operate in common as a parallel link. In the serial mode, input and output controls are received independently for each link; during the parallel mode, a single set of input and output controls is used in common by all of the links.
摘要翻译：要解决的问题：提供允许使用串行访问或并行访问来执行访问一个或多个存储体的方法和系统。解决方案：在串行模式下，每个链路作为独立的串行链路工作。相反，在并行模式下，链路作为并行链路共同工作。在串行模式下，为每个链路独立接收输入和输出控制; 在并行模式下，所有链接共同使用一组输入和输出控件。

5. 发明专利

JP2013080560A Dynamic random access memory with fully independent partial array refresh function 审中-公开
标题翻译：具有完全独立部分阵列刷新功能的动态随机访问记忆
公开(公告)号：JP2013080560A
公开(公告)日：2013-05-02
申请号：JP2012287266
申请日：2012-12-28
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI , HAKJUNE OH
IPC分类号： G11C11/406 , G11C11/403
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
摘要： PROBLEM TO BE SOLVED: To provide improved dynamic random access memory (DRAM) including an independent partial array refresh function.SOLUTION: A DRAM device includes a plurality of memory subblocks. Each subblock includes a plurality of word lines to which a plurality of data storage cells are connected. Partial array self-refresh (PASR) configuration setting is independently made. The memory subblocks are addressed for refreshing, according to the PASR setting. The PASR setting is made by a memory controller. All kinds of combinations of subblock addresses are selectable. Thus, the memory subblocks are fully and independently refreshed. User selectable memory arrays for data storing provide effective memory control programming especially for low power consumption mobile application.
摘要翻译：要解决的问题：提供包括独立的部分阵列刷新功能的改进的动态随机存取存储器（DRAM）。解决方案：DRAM设备包括多个存储器子块。每个子块包括连接多个数据存储单元的多个字线。部分阵列自刷新（PASR）配置设置是独立制作的。根据PASR设置，存储器子块被寻址以进行刷新。 PASR设置由内存控制器进行。子块地址的各种组合可以选择。因此，存储器子块被完全和独立地刷新。用于数据存储的用户可选存储阵列提供有效的存储器控制编程，特别是对于低功耗移动应用。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2012181916A Multiple independent serial link memory 审中-公开
标题翻译：多个独立的串行链路存储器
公开(公告)号：JP2012181916A
公开(公告)日：2012-09-20
申请号：JP2012116380
申请日：2012-05-22
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI , PYEON HONG BEOM
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： PROBLEM TO BE SOLVED: To provide an apparatus, system, and method for controlling data transfer between serial data link interfaces and memory banks in a semiconductor memory.SOLUTION: In one example, a flash memory device with multiple serial data links and multiple memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between the memory devices. In addition, a virtual multiple link configuration is described where a single link is used to emulate multiple links.
摘要翻译：要解决的问题：提供一种用于控制半导体存储器中的串行数据链路接口和存储体之间的数据传输的装置，系统和方法。解决方案：在一个示例中，公开了具有多个串行数据链路的闪存器件和多个存储器组，其中链路独立于存储体。闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。另外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2012178190A Independent link and bank selection 有权
标题翻译：独立链接和银行选择
公开(公告)号：JP2012178190A
公开(公告)日：2012-09-13
申请号：JP2012136668
申请日：2012-06-18
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： PYEON HONG BEOM , OH HAK JUNE , KIM JIN-KI
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G06F13/4022 , G11C7/1048 , G11C7/18 , G11C11/408
摘要： PROBLEM TO BE SOLVED: To provide a memory system that includes a plurality of memory banks and a plurality of link controllers.SOLUTION: The memory system include, for each memory bank, first switching logic for receiving an output for each link controller, and for conveying the output of only one of the link controllers to the memory bank. In addition, the memory system, for each link controller, second switching logic for receiving an output of each of the memory banks, and for conveying the output of only one of the memory banks to the link controller. According to an embodiment of the invention, the memory system include switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access to the same memory bank by the plurality of link controllers and prevent simultaneous or overlapping access to the plurality of banks by the same link controller.
摘要翻译：要解决的问题：提供一种包括多个存储器组和多个链路控制器的存储器系统。解决方案：对于每个存储体，存储器系统包括用于接收每个链路控制器的输出以及仅将一个链路控制器的输出传送到存储体的第一切换逻辑。此外，对于每个链路控制器，存储器系统用于接收每个存储体的输出的第二切换逻辑，以及仅将一个存储体的输出传送到链路控制器。根据本发明的实施例，存储器系统包括用于控制第一开关逻辑和第二开关逻辑的操作的开关控制器逻辑，以防止由多个链路控制器同时或重叠地访问同一个存储体，并且防止同时或通过相同的链路控制器重叠访问多个银行。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2014032738A Nand flash memory having a plurality of cell substrates 审中-公开
标题翻译：具有多种细胞基底的NAND FLASH存储器
公开(公告)号：JP2014032738A
公开(公告)日：2014-02-20
申请号：JP2013238531
申请日：2013-11-19
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a method for operating a NAND flash device.SOLUTION: The method for selectively giving an erasure voltage to the NAND flash device having a first well sector, a second well sector and at least one memory block respectively formed in the first well sector and the second well sector includes: a step of selecting one of the two memory blocks to erase a NAND cell string in response to a block address; a step of selecting the first well sector in response to at least a part of the block address; and a step of applying the erasure voltage to the first well sector.
摘要翻译：要解决的问题：提供一种用于操作NAND闪存器件的方法。解决方案：用于向具有第一阱扇区，第二阱扇区和至少一个存储器块的NAND闪存器件选择性地给出擦除电压的方法分别形成在第一阱扇区和第二阱区包括：响应于块地址而选择两个存储块之一来擦除NAND单元串的步骤; 响应于块地址的至少一部分来选择第一阱扇区的步骤; 以及将擦除电压施加到第一阱扇区的步骤。

9. 发明专利

JP2013239210A Id generation apparatus and method for serially interconnected devices 审中-公开
标题翻译： ID生成装置和用于串行互连装置的方法
公开(公告)号：JP2013239210A
公开(公告)日：2013-11-28
申请号：JP2013183052
申请日：2013-09-04
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： PYEON HONG BEOM , OH HAK JUNE , KIM JIN-KI , STEVEN A PRZYBYLSKI
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G11C7/20 , G06F13/4291 , G11C7/10 , G11C7/1003 , G11C19/00 , G11C2029/4402
摘要： PROBLEM TO BE SOLVED: To provide an apparatus and method for recognizing the number of serially connected devices and output latency of serially interconnected devices.SOLUTION: An embodiment comprises a plurality of memory devices in a serial interconnection configuration, and a receiver. Each of the plurality of memory devices has an input connection and an output connection. The input connection and the output connection of each device are respectively coupled to the output connection of its previous device and the input connection of its next device. Each of the plurality of memory devices includes a generator for generating a device identifier (ID). The ID generated by each device is provided to its next device. The receiver receives the ID from a last device of the serial interconnection configuration, and determines latency of the serial interconnection configuration of the plurality of memory devices.
摘要翻译：要解决的问题：提供用于识别串行连接的设备的数量和串行互连设备的输出等待时间的装置和方法。解决方案：实施例包括串行互连配置中的多个存储器件和接收器。多个存储器件中的每一个具有输入连接和输出连接。每个设备的输入连接和输出连接分别耦合到其先前设备的输出连接和其下一个设备的输入连接。多个存储器件中的每一个包括用于产生器件标识符（ID）的发生器。每个设备生成的ID被提供给其下一个设备。接收器从串行互连配置的最后一个设备接收ID，并确定多个存储设备的串行互连配置的等待时间。

10. 发明专利

JP2012226786A Scalable memory system 审中-公开
标题翻译：可扩展存储系统
公开(公告)号：JP2012226786A
公开(公告)日：2012-11-15
申请号：JP2012182111
申请日：2012-08-21
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI , PARK JUNG-OH , PYEON HONG BEOM , STEVEN PRZYBYLSKI
IPC分类号： G06F12/00 , G06F12/04 , G06F12/06 , G06F13/16
CPC分类号： G11C7/1042 , G11C7/10 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C8/04 , G11C16/0483
摘要： PROBLEM TO BE SOLVED: To provide a memory system architecture capable of supporting any number of memory devices.SOLUTION: A memory system includes a plurality of series-connected memory devices. Each memory device includes a series input/output interface between other memory devices and a memory controller, which outputs a command in a bit stream, the bit stream conforming to a modular command protocol. The command includes an operation code as well as address information and a device address, and only an addressed memory device operates on the command. A data output strobe signal and a command input strobe signal are supplied in parallel with respective output data streams and an input command data stream so as to identify a type and a length of data. The modular command protocol is used for simultaneous operations in the respective memory devices for performance improvement.
摘要翻译：要解决的问题：提供能够支持任何数量的存储器件的存储器系统架构。解决方案：存储器系统包括多个串联存储器件。每个存储器件包括在其它存储器件和存储器控制器之间的串联输入/输出接口，存储器控制器输出符合模块化命令协议的比特流中的命令。该命令包括操作代码以及地址信息和设备地址，并且只有寻址的存储器件对该命令进行操作。数据输出选通信号和命令输入选通信号与相应的输出数据流和输入命令数据流并行提供，以便识别数据的类型和长度。模块化命令协议用于各个存储器件中的同时操作，以提高性能。版权所有（C）2013，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式