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    • 9. 发明授权
    • Direct memory access controller for reducing access time to transfer
information from a disk
    • 直接内存访问控制器,用于减少从磁盘传输信息的访问时间
    • US4723223A
    • 1988-02-02
    • US731941
    • 1985-05-08
    • Masayuki Hanada
    • Masayuki Hanada
    • G06F12/08G06F13/28G06F13/04
    • G06F13/28G06F12/0866
    • A direct memory access controller, such as for a disk, includes address registers containing beginning and end addresses defining a transfer area of a disk, a location counter which points to a specific location which is being accessed in the transfer area, updating circuitry to set the location counter to the initial address after the location corresponding to the end address has been accessed, and termination circuitry for disabling the location counter when all of the memory locations of the transfer area have been accessed. The address initially loaded into the location counter is for the location which can be accessed most quickly by the direct memory access controller.
    • 诸如用于磁盘的直接存储器访问控制器包括地址寄存器,其包含限定盘的传送区域的开始和结束地址,指向在传送区域中被访问的特定位置的位置计数器,更新电路以设置 已经访问了与结束地址相对应的位置之后的初始地址的位置计数器,并且已经访问了传输区域的所有存储器位置时禁止位置计数器的终止电路。 最初加载到位置计数器中的地址是由直接存储器访问控制器最快速访问的位置。
    • 10. 发明授权
    • Data transfer control unit permitting data access to memory prior to
completion of data transfer
    • 数据传输控制单元允许在数据传输完成之前对存储器进行数据访问
    • US4864533A
    • 1989-09-05
    • US913762
    • 1986-09-30
    • Masayuki Hanada
    • Masayuki Hanada
    • G06F13/12G06F13/28
    • G06F13/28
    • A data transfer control unit comprises a first address register, a second address register and a control circuit. The first address register stores a first final address value of a memory area of a memory into which data is to be transferred. The second address register stores a second final address value of data which has already been transferred to the memory area of the memory. The control circuit compares the first final address value and a second final address value with an address value of data access by a CPU in order to generate a memory indication signal indicative of whether the address value of data accessed by the CPU belongs to the addresses of the data which has already been stored or has not yet been stored. The control circuit further prohibits a data transfer from the memory area to the CPU only when the address value of the data accessed by the CPU belongs to the addresses of the data which have not yet been stored in the memory.
    • 数据传送控制单元包括第一地址寄存器,第二地址寄存器和控制电路。 第一地址寄存器存储要传送数据的存储器的存储区域的第一最终地址值。 第二地址寄存器存储已经传送到存储器的存储区域的数据的第二个最终地址值。 控制电路将第一最终地址值和第二最终地址值与CPU的数据访问地址值进行比较,以便产生指示由CPU访问的数据的地址值是否属于 已经存储或尚未存储的数据。 只有当CPU访问的数据的地址值属于尚未存储在存储器中的数据的地址时,控制电路进一步禁止从存储器区域到CPU的数据传输。