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1. 发明授权

US08519803B2 Resonator systems and methods for tuning resonator systems 有权
标题翻译：用于调谐谐振器系统的谐振器系统和方法
公开(公告)号：US08519803B2
公开(公告)日：2013-08-27
申请号：US12915598
申请日：2010-10-29
申请人： Moray McLaren , Raymond G. Beausoleil , Marco Fiorentino , Nathan Lorenzo Binkert , Norman Paul Jouppi , Alan Lynn Davis
发明人： Moray McLaren , Raymond G. Beausoleil , Marco Fiorentino , Nathan Lorenzo Binkert , Norman Paul Jouppi , Alan Lynn Davis
IPC分类号： H04B10/02 , G02B6/12 , G02B6/26 , H04J14/02
CPC分类号： H01P7/088 , G02F1/0147 , G02F2203/15 , H01P1/2084
摘要： Tunable resonator systems and methods for tuning resonator systems are disclosed. In one aspect, a resonator system includes an array of resonators disposed adjacent to a waveguide, at least one temperature sensor located adjacent to the array of resonators, and a resonator control electronically connected to the at least one temperature sensor. Each resonator has a resonance frequency in a resonator frequency comb and channels with frequencies in a channel frequency comb are transmitted in the waveguide. Resonance frequencies in the resonator frequency comb are to be adjusted in response to ambient temperature changes detected by the at least one temperature sensors to align the resonance frequency comb with the channel frequency comb.
摘要翻译：公开了可调谐谐振器系统和用于调谐谐振器系统的方法。在一个方面，谐振器系统包括邻近波导设置的谐振器阵列，与谐振器阵列相邻的至少一个温度传感器，以及电连接到至少一个温度传感器的谐振器控制器。每个谐振器在谐振器频率梳中具有谐振频率，并且在波导中传输具有信道频率梳中的频率的信道。要响应于由至少一个温度传感器检测到的环境温度变化来调节谐振器频率梳中的谐振频率，以使谐振频率梳与通道频率梳对齐。

2. 发明申请

US20120105177A1 RESONATOR SYSTEMS AND METHODS FOR TUNING RESONATOR SYSTEMS 有权
标题翻译：用于调谐谐振器系统的谐振器系统和方法
公开(公告)号：US20120105177A1
公开(公告)日：2012-05-03
申请号：US12915598
申请日：2010-10-29
申请人： Moray McLaren , Raymond G. Beausoleil , Marco Fiorentino , Nathan Lorenzo Binkert , Norman Paul Jouppi , Alan Lynn Davis
发明人： Moray McLaren , Raymond G. Beausoleil , Marco Fiorentino , Nathan Lorenzo Binkert , Norman Paul Jouppi , Alan Lynn Davis
IPC分类号： H04B3/04 , H01P7/00
CPC分类号： H01P7/088 , G02F1/0147 , G02F2203/15 , H01P1/2084
摘要： Tunable resonator systems and methods for tuning resonator systems are disclosed. In one aspect, a resonator system includes an array of resonators disposed adjacent to a waveguide, at least one temperature sensor located adjacent to the array of resonators, and a resonator control electronically connected to the at least one temperature sensor. Each resonator has a resonance frequency in a resonator frequency comb and channels with frequencies in a channel frequency comb are transmitted in the waveguide. Resonance frequencies in the resonator frequency comb are to be adjusted in response to ambient temperature changes detected by the at least one temperature sensors to align the resonance frequency comb with the channel frequency comb.
摘要翻译：公开了可调谐谐振器系统和用于调谐谐振器系统的方法。在一个方面，谐振器系统包括邻近波导设置的谐振器阵列，与谐振器阵列相邻的至少一个温度传感器，以及电连接到至少一个温度传感器的谐振器控制器。每个谐振器在谐振器频率梳中具有谐振频率，并且在波导中传输具有信道频率梳中的频率的信道。要响应于由至少一个温度传感器检测到的环境温度变化来调节谐振器频率梳中的谐振频率，以使谐振频率梳与通道频率梳对齐。

3. 发明申请

US20110286743A1 FLOW-CONTROL METHODS AND SYSTEMS FOR MULTIBUS SYSTEMS 有权
标题翻译：多通道系统的流量控制方法和系统
公开(公告)号：US20110286743A1
公开(公告)日：2011-11-24
申请号：US12785962
申请日：2010-05-24
申请人： Moray McLaren , Nathan Lorenzo Binkert , Alan Lynn Davis , Norman Paul Jouppi
发明人： Moray McLaren , Nathan Lorenzo Binkert , Alan Lynn Davis , Norman Paul Jouppi
IPC分类号： H04J14/00 , H04L12/26
CPC分类号： H04B10/278 , H04J14/028 , H04L47/13
摘要： Methods and systems are provided that prevent buffer overflow in multibus systems. In one aspect, a method for controlling the flow of data in a multibus system includes, for each node having an associated broadcast bus in the multibus system, generating status information regarding available data storage space of each receive buffer of the node. The method includes broadcasting the status information to the other nodes connected to the broadcast bus and collecting status information regarding the available storage space of receive buffers of the other nodes connected to the broadcast bus. The method also includes determining whether or not to send data from the node to at least one of the other nodes over the broadcast bus based on the collected status information.
摘要翻译：提供了防止多总线系统中的缓冲区溢出的方法和系统。在一个方面，一种用于控制多巴系统中的数据流的方法包括：对于在所述多总线系统中具有相关联的广播总线的每个节点，生成关于所述节点的每个接收缓冲器的可用数据存储空间的状态信息。该方法包括将状态信息广播到连接到广播总线的其他节点，并且收集与连接到广播总线的其他节点的接收缓冲器的可用存储空间有关的状态信息。该方法还包括基于收集的状态信息来确定是否通过广播总线从节点向至少一个其他节点发送数据。

4. 发明授权

US08391717B2 Flow-control methods and systems for multibus systems 有权
标题翻译：多轴系统的流量控制方法和系统
公开(公告)号：US08391717B2
公开(公告)日：2013-03-05
申请号：US12785962
申请日：2010-05-24
申请人： Moray McLaren , Nathan Lorenzo Binkert , Alan Lynn Davis , Norman Paul Jouppi
发明人： Moray McLaren , Nathan Lorenzo Binkert , Alan Lynn Davis , Norman Paul Jouppi
IPC分类号： H04J14/00
CPC分类号： H04B10/278 , H04J14/028 , H04L47/13
摘要： Methods and systems are provided that prevent buffer overflow in multibus systems. In one aspect, a method for controlling the flow of data in a multibus system includes, for each node having an associated broadcast bus in the multibus system, generating status information regarding available data storage space of each receive buffer of the node. The method includes broadcasting the status information to the other nodes connected to the broadcast bus and collecting status information regarding the available storage space of receive buffers of the other nodes connected to the broadcast bus. The method also includes determining whether or not to send data from the node to at least one of the other nodes over the broadcast bus based on the collected status information.
摘要翻译：提供了防止多总线系统中的缓冲区溢出的方法和系统。在一个方面，一种用于控制多巴系统中的数据流的方法包括：对于在所述多总线系统中具有相关联的广播总线的每个节点，生成关于所述节点的每个接收缓冲器的可用数据存储空间的状态信息。该方法包括将状态信息广播到连接到广播总线的其他节点，并且收集与连接到广播总线的其他节点的接收缓冲器的可用存储空间有关的状态信息。该方法还包括基于收集的状态信息来确定是否通过广播总线从节点向至少一个其他节点发送数据。

5. 发明授权

US08059443B2 Three-dimensional memory module architectures 有权
标题翻译：三维内存模块架构
公开(公告)号：US08059443B2
公开(公告)日：2011-11-15
申请号：US11975963
申请日：2007-10-23
申请人： Moray McLaren , Jung Ho Ahn , Alan Lynn Davis , Nathan Lorenzo Binkert , Norman Paul Jouppi
发明人： Moray McLaren , Jung Ho Ahn , Alan Lynn Davis , Nathan Lorenzo Binkert , Norman Paul Jouppi
IPC分类号： G11C13/04
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C13/04 , G11C2211/4016 , G11C2213/71 , H01L25/0657 , H01L25/18 , H01L2225/06534 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.
摘要翻译：本发明的各种实施例涉及堆叠的存储器模块。在本发明的一个实施例中，存储器模块包括至少一个堆叠有至少一个存储器层的存储器 - 控制器层。通过通孔（例如，通过硅通孔）精细地延伸通过堆叠大致垂直于至少一个存储器控制器的表面延伸，从而提供至少一个存储器控制器与至少一个存储器层之间的电子通信。此外，存储器控制器层包括被配置为向存储器模块传送数据和从存储器模块传送数据的至少一个外部接口。此外，存储器模块可以包括光学层。光学层可以被包括在堆叠中并且具有总线波导以将数据传送到至少一个存储器控制器和从至少一个存储器控制器传送数据。外部接口可以是与光学层接口的光学外部接口。

6. 发明授权

US08335434B2 All optical fast distributed arbitration in a computer system device 有权
标题翻译：所有光学快速分布式仲裁在计算机系统设备中
公开(公告)号：US08335434B2
公开(公告)日：2012-12-18
申请号：US12682918
申请日：2008-10-23
申请人： Raymond G. Beausoleil , Marco Fiorentino , Norman Paul Jouppi , Nathan Lorenzo Binkert , Robert Samuel Schreiber , Qianfan Xu
发明人： Raymond G. Beausoleil , Marco Fiorentino , Norman Paul Jouppi , Nathan Lorenzo Binkert , Robert Samuel Schreiber , Qianfan Xu
IPC分类号： H04B10/20 , H04B10/04 , H04J14/02
CPC分类号： G02B6/43 , G02B6/12007 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L31/101 , H01L2224/13025 , H01L2224/451 , H01L2224/48091 , H01L2224/73253 , H01L2224/73265 , H01L2225/06541 , H01L2924/01019 , H01L2924/01068 , H01L2924/12043 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： Various embodiments of the present invention are directed to systems and methods for all optical distributed arbitration for computer system components (1801-1804) communicatively coupled via a photonic interconnect in a computer system device. The embodiments of the optical arbitration in the computer system provides arbitration schemes with fixed priority (2000) and non-fixed priority (1830, 2200). The non-fixed priority scheme embodiments can provide fairness in arbitration. In some embodiments, delivery of light power and arbitration are combined (1830, 2001).
摘要翻译：本发明的各种实施例涉及用于计算机系统组件（1801-1804）的所有光分布式仲裁的系统和方法，所述计算机系统组件通过计算机系统设备中的光子互连通信地耦合。计算机系统中的光学仲裁的实施例提供具有固定优先级（2000）和非固定优先级（1830,2200）的仲裁方案。非固定优先权方案实施例可以在仲裁中提供公平性。在一些实施例中，组合光功率和仲裁的传递（1830,2001）。

7. 发明授权

US07889956B2 Photonic interconnects for computer system devices 有权
标题翻译：用于计算机系统设备的光子互连
公开(公告)号：US07889956B2
公开(公告)日：2011-02-15
申请号：US12387216
申请日：2009-04-29
申请人： Raymond G. Beausoleil , Marco Fiorentino , Norman Paul Jouppi , Nathan Lorenzo Binkert , Robert Samuel Schreiber , Qianfan Xu
发明人： Raymond G. Beausoleil , Marco Fiorentino , Norman Paul Jouppi , Nathan Lorenzo Binkert , Robert Samuel Schreiber , Qianfan Xu
IPC分类号： G02B6/12
CPC分类号： G02B6/43 , H04B10/801
摘要： Various embodiments of the present invention are directed to photonic interconnects that can be used for on-chip as well as off-chip communications between computer system components. In one embodiment of the present invention, a photonic interconnect comprises a plurality of on-chip waveguides. Additionally, the photonic interconnect may include a plurality of off-chip waveguides, and at least one optoelectronic converter. The at least one optoelectronic converter can be photonically coupled to a portion of the plurality of on-chip waveguides, can be photonically coupled to a portion of the plurality of off-chip waveguides, and is in electronic communication with at least one computer system component.
摘要翻译：本发明的各种实施例涉及可用于片上以及计算机系统部件之间的片外通信的光子互连。在本发明的一个实施例中，光子互连包括多个片上波导。另外，光子互连可以包括多个片外波导，以及至少一个光电转换器。所述至少一个光电转换器可以光子耦合到所述多个片上波导的一部分，可光子耦合到所述多个芯片外波导的一部分，并且与至少一个计算机系统组件进行电子通信。

8. 发明申请

US20090103854A1 Photonic interconnects for computer system devices 有权
公开(公告)号：US20090103854A1
公开(公告)日：2009-04-23
申请号：US11975974
申请日：2007-10-23
申请人： Raymond G. Beausoleil , Marco Fiorentino , Norman Paul Jouppi , Nathan Lorenzo Binkert , Robert Samuel Schreiber , Qianfan Xu
发明人： Raymond G. Beausoleil , Marco Fiorentino , Norman Paul Jouppi , Nathan Lorenzo Binkert , Robert Samuel Schreiber , Qianfan Xu
IPC分类号： G02B6/12
CPC分类号： G02B6/43 , H04B10/801
摘要： Various embodiments of the present invention are directed to photonic interconnects that can be used for on-chip as well as off-chip communications between computer system components. In one embodiment of the present invention, a photonic interconnect comprises a plurality of on-chip waveguides. Additionally, the photonic interconnect may include a plurality of off-chip waveguides, and at least one optoelectronic converter. The at least one optoelectronic converter can be photonically coupled to a portion of the plurality of on-chip waveguides, can be photonically coupled to a portion of the plurality of off-chip waveguides, and is in electronic communication with at least one computer system component.

9. 发明申请

US20090103345A1 Three-dimensional memory module architectures 有权
标题翻译：三维内存模块架构
公开(公告)号：US20090103345A1
公开(公告)日：2009-04-23
申请号：US11975963
申请日：2007-10-23
申请人： Moray McLaren , Jung Ho Ahn , Alan Lynn Davis , Nathan Lorenzo Binkert , Norman Paul Jouppi
发明人： Moray McLaren , Jung Ho Ahn , Alan Lynn Davis , Nathan Lorenzo Binkert , Norman Paul Jouppi
IPC分类号： G11C5/06 , G11C13/04
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C13/04 , G11C2211/4016 , G11C2213/71 , H01L25/0657 , H01L25/18 , H01L2225/06534 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.
摘要翻译：本发明的各种实施例涉及堆叠的存储器模块。在本发明的一个实施例中，存储器模块包括至少一个堆叠有至少一个存储器层的存储器 - 控制器层。通过通孔（例如，通过硅通孔）精细地延伸通过堆叠大致垂直于至少一个存储器控制器的表面延伸，从而提供至少一个存储器控制器与至少一个存储器层之间的电子通信。此外，存储器控制器层包括被配置为向存储器模块传送数据和从存储器模块传送数据的至少一个外部接口。此外，存储器模块可以包括光学层。光学层可以被包括在堆叠中并且具有总线波导以将数据传送到至少一个存储器控制器和从至少一个存储器控制器传送数据。外部接口可以是与光学层接口的光学外部接口。

10. 发明申请

US20130318325A1 COMPOSITE PROCESSORS 有权
标题翻译：复合处理器
公开(公告)号：US20130318325A1
公开(公告)日：2013-11-28
申请号：US13978039
申请日：2011-01-20
申请人： Raymond G. Beausoleil , Marco Fiorentino , Moray McLaren , Greg Astfalk , Nathan Lorenzo Binkert , David A. Fattal
发明人： Raymond G. Beausoleil , Marco Fiorentino , Moray McLaren , Greg Astfalk , Nathan Lorenzo Binkert , David A. Fattal
IPC分类号： G06F15/80
CPC分类号： G06F15/80 , G06E3/00 , G06F3/00 , G06F13/4063
摘要： In one example, a composite processor (100) includes a circuit board (1200), a first processor element package (1230), and a second processor element package (1240). The circuit board has an optical link (1211) and an electrical link (1221). The first processor element package (1230) includes a substrate (1231) with an integrated circuit (240), a sub-wavelength grating optical coupler (1232), and an electrical coupler (1233) coupled to the electrical link (1221) of the circuit board (1200). The second processor element package (1240) includes a substrate (1241) with an integrated circuit (240), a sub-wavelength grating optical coupler (1242), and an electrical coupler (1243) coupled to the electrical link (1221) of the circuit board (1220). The sub-wavelength grating optical coupler (1232) of the first processor element package (1230), the optical link (1211) of the circuit board (1220), and the sub-wavelength grating optical coupler (1242) of the second processor element package (1240) collectively define an optical communications path (1270) between the substrate (1231) of the first processor element package (1230) and the substrate (1241) of the second processor element package (1240).
摘要翻译：在一个示例中，复合处理器（100）包括电路板（1200），第一处理器元件封装（1230）和第二处理器元件封装（1240）。电路板具有光学链路（1211）和电连接（1221）。第一处理器元件封装（1230）包括具有集成电路（240）的基板（1231），子波长光栅光耦合器（1232）和耦合到所述电连接器（1221）的电耦合器（1233）电路板（1200）。第二处理器元件封装（1240）包括具有集成电路（240）的基板（1241），子波长光栅光耦合器（1242）和耦合到所述电连接器（1221）的电耦合器（1243）电路板（1220）。第一处理器元件封装（1230）的子波长光栅光耦合器（1232），电路板（1220）的光链路（1211）以及第二处理器元件的子波长光栅光耦合器（1242）封装（1240）共同地限定了第一处理器元件封装（1230）的衬底（1231）与第二处理器元件封装（1240）的衬底（1241）之间的光通信路径（1270）。

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