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1. 发明申请

US20090227116A1 Method for Manufacturing Non-Volatile Memory Device having Charge Trap Layer 失效
标题翻译：制造具有电荷陷阱层的非易失性存储器件的方法
公开(公告)号：US20090227116A1
公开(公告)日：2009-09-10
申请号：US12347289
申请日：2008-12-31
申请人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi , Sung Jin Whang
发明人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi , Sung Jin Whang
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/513 , H01L29/792
摘要： A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.
摘要翻译：制造具有电荷陷阱层的非易失性存储器件的方法包括在一个实施例中：在半导体衬底上形成第一介电层; 在所述第一介电层上形成具有比所述第一介电层的介电常数更高的介电常数的第二电介质层; 形成用于防止所述第二介电层上的界面反应的氮化物缓冲层; 通过向所述氮化物缓冲层上提供自由基氧化源以氧化所述氮化物缓冲层而形成第三电介质层，从而形成包括所述第一，第二和第三电介质层的隧道层; 并在隧道层上形成电荷陷阱层，屏蔽层和控制栅极电极层。

2. 发明授权

US07736975B2 Method for manufacturing non-volatile memory device having charge trap layer 失效
标题翻译：具有电荷陷阱层的非易失性存储器件的制造方法
公开(公告)号：US07736975B2
公开(公告)日：2010-06-15
申请号：US12347289
申请日：2008-12-31
申请人： Won Joon Choi , Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Sung Jin Whang
发明人： Won Joon Choi , Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Sung Jin Whang
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/513 , H01L29/792
摘要： A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.
摘要翻译：制造具有电荷陷阱层的非易失性存储器件的方法包括在一个实施例中：在半导体衬底上形成第一介电层; 在所述第一介电层上形成具有比所述第一介电层的介电常数更高的介电常数的第二电介质层; 形成用于防止所述第二介电层上的界面反应的氮化物缓冲层; 通过向所述氮化物缓冲层上提供自由基氧化源以氧化所述氮化物缓冲层而形成第三电介质层，从而形成包括所述第一，第二和第三电介质层的隧道层; 并在隧道层上形成电荷陷阱层，屏蔽层和控制栅极电极层。

3. 发明授权

US07824992B2 Method of fabricating non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07824992B2
公开(公告)日：2010-11-02
申请号：US12345785
申请日：2008-12-30
申请人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi
发明人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L21/3145 , H01L21/31645 , H01L21/76224 , H01L29/513 , H01L29/518 , H01L29/7881
摘要： A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.
摘要翻译：制造非易失性存储器件的方法包括：在半导体衬底上形成隧道绝缘层图案和浮栅电极层图案; 通过蚀刻半导体衬底的暴露部分形成隔离沟槽，使得隔离沟槽与隧道绝缘层图案和浮栅电极层图案对准; 通过用填充绝缘层填充隔离沟槽来形成隔离层; 在隔离层和浮栅电极层图案上形成富铪铪氧化硅层; 通过在富铪铪氧化硅层上进行第一次氮化，形成富铪铪硅氮化物层; 在富铪铪硅氮化物层上形成富硅铪氧化硅层; 通过在富硅铪氧化硅层上进行第二次氮化，形成富硅铪硅氮氧化物层; 以及在所述富硅铪硅氮氧化物层上形成控制栅电极层。

4. 发明授权

US08105909B2 Method of fabricating non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08105909B2
公开(公告)日：2012-01-31
申请号：US12894021
申请日：2010-09-29
申请人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi
发明人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L21/3145 , H01L21/31645 , H01L21/76224 , H01L29/513 , H01L29/518 , H01L29/7881
摘要： A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.
摘要翻译：制造非易失性存储器件的方法包括：在半导体衬底上形成隧道绝缘层图案和浮栅电极层图案; 通过蚀刻半导体衬底的暴露部分形成隔离沟槽，使得隔离沟槽与隧道绝缘层图案和浮栅电极层图案对准; 通过用填充绝缘层填充隔离沟槽来形成隔离层; 在隔离层和浮栅电极层图案上形成富铪铪氧化硅层; 通过在富铪铪氧化硅层上进行第一次氮化，形成富铪铪硅氮化物层; 在富铪铪硅氮化物层上形成富硅铪氧化硅层; 通过在富硅铪氧化硅层上进行第二次氮化，形成富硅铪硅氮氧化物层; 以及在所述富硅铪硅氮氧化物层上形成控制栅电极层。

5. 发明申请

US20110014759A1 Method of Fabricating Non-volatile Memory Device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20110014759A1
公开(公告)日：2011-01-20
申请号：US12894021
申请日：2010-09-29
申请人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi
发明人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/3145 , H01L21/31645 , H01L21/76224 , H01L29/513 , H01L29/518 , H01L29/7881
摘要： A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.
摘要翻译：制造非易失性存储器件的方法包括：在半导体衬底上形成隧道绝缘层图案和浮栅电极层图案; 通过蚀刻半导体衬底的暴露部分形成隔离沟槽，使得隔离沟槽与隧道绝缘层图案和浮栅电极层图案对准; 通过用填充绝缘层填充隔离沟槽来形成隔离层; 在隔离层和浮栅电极层图案上形成富铪铪氧化硅层; 通过在富铪铪氧化硅层上进行第一次氮化，形成富铪铪硅氮化物层; 在富铪铪硅氮化物层上形成富硅铪氧化硅层; 通过在富硅铪氧化硅层上进行第二次氮化，形成富硅铪硅氮氧化物层; 以及在所述富硅铪硅氮氧化物层上形成控制栅电极层。

6. 发明申请

US20090253242A1 Method of Fabricating Non-Volatile Memory Device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090253242A1
公开(公告)日：2009-10-08
申请号：US12345785
申请日：2008-12-30
申请人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi
发明人： Moon Sig Joo , Heung Jae Cho , Yong Soo Kim , Won Joon Choi
IPC分类号： H01L21/762 , H01L21/4763
CPC分类号： H01L21/28273 , H01L21/3145 , H01L21/31645 , H01L21/76224 , H01L29/513 , H01L29/518 , H01L29/7881
摘要： A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.
摘要翻译：制造非易失性存储器件的方法包括：在半导体衬底上形成隧道绝缘层图案和浮栅电极层图案; 通过蚀刻半导体衬底的暴露部分形成隔离沟槽，使得隔离沟槽与隧道绝缘层图案和浮栅电极层图案对准; 通过用填充绝缘层填充隔离沟槽来形成隔离层; 在隔离层和浮栅电极层图案上形成富铪铪氧化硅层; 通过在富铪铪氧化硅层上进行第一次氮化，形成富铪铪硅氮化物层; 在富铪铪硅氮化物层上形成富硅铪氧化硅层; 通过在富硅铪氧化硅层上进行第二次氮化，形成富硅铪硅氮氧化物层; 以及在所述富硅铪硅氮氧化物层上形成控制栅电极层。

7. 发明申请

US20090004802A1 METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE HAVING CHARGE TRAPPING LAYER 失效
标题翻译：制造具有电荷捕获层的非易失性存储器件的方法
公开(公告)号：US20090004802A1
公开(公告)日：2009-01-01
申请号：US11966231
申请日：2007-12-28
申请人： Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
发明人： Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , Y10S438/942
摘要： A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.
摘要翻译：一种制造具有电荷捕获层的非易失性存储器件的方法包括在衬底上形成隧道层，电荷俘获层，阻挡层和控制栅电极层，在控制栅电极层上形成掩模层图案使用掩模层图案作为蚀刻掩模进行蚀刻处理以去除控制栅电极层的暴露部分，其中蚀刻工艺作为过度蚀刻进行，以将电荷捕获层除去指定厚度，形成绝缘层用于阻止电荷在控制栅电极层和掩模层图案上移动，对绝缘层进行各向异性蚀刻，以在控制栅电极层的侧壁和阻挡层的一部分上侧壁上形成绝缘层图案，以及对通过各向异性蚀刻暴露的阻挡层进行蚀刻处理，其中执行蚀刻处理作为过量蚀刻以将电荷捕获层除去指定的厚度。

8. 发明授权

US07981786B2 Method of fabricating non-volatile memory device having charge trapping layer 失效
标题翻译：制造具有电荷捕获层的非易失性存储器件的方法
公开(公告)号：US07981786B2
公开(公告)日：2011-07-19
申请号：US11966231
申请日：2007-12-28
申请人： Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
发明人： Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , Y10S438/942
摘要： A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.
摘要翻译：一种制造具有电荷捕获层的非易失性存储器件的方法包括在衬底上形成隧道层，电荷俘获层，阻挡层和控制栅电极层，在控制栅电极层上形成掩模层图案使用掩模层图案作为蚀刻掩模进行蚀刻处理以去除控制栅电极层的暴露部分，其中蚀刻工艺作为过度蚀刻进行，以将电荷捕获层除去指定厚度，形成绝缘层用于阻止电荷在控制栅电极层和掩模层图案上移动，对绝缘层进行各向异性蚀刻，以在控制栅电极层的侧壁和阻挡层的一部分上侧壁上形成绝缘层图案，以及对通过各向异性蚀刻暴露的阻挡层进行蚀刻处理，其中执行蚀刻处理作为过量蚀刻以将电荷捕获层除去指定的厚度。

9. 发明授权

US08294200B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08294200B2
公开(公告)日：2012-10-23
申请号：US13089865
申请日：2011-04-19
申请人： Moon Sig Joo , Seung Ho Pyi , Yong Soo Kim
发明人： Moon Sig Joo , Seung Ho Pyi , Yong Soo Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28282
摘要： A non-volatile memory device includes a substrate, a tunneling layer over the substrate, a charge trapping layer including a nitride layer and a silicon boron nitride layer over the tunneling layer, and a blocking layer over the charge trapping layer, and a control gate electrode arranged on the blocking layer.
摘要翻译：非易失性存储器件包括衬底，衬底上的隧道层，在隧穿层上方包括氮化物层和氮化硼氮化物层的电荷俘获层，以及电荷俘获层上的阻挡层，以及控制栅极电极布置在阻挡层上。

10. 发明授权

US07948025B2 Non-volatile memory device having charge trapping layer and method for fabricating the same 有权
标题翻译：具有电荷捕获层的非易失性存储器件及其制造方法
公开(公告)号：US07948025B2
公开(公告)日：2011-05-24
申请号：US11770985
申请日：2007-06-29
申请人： Moon Sig Joo , Seung Ho Pyi , Yong Soo Kim
发明人： Moon Sig Joo , Seung Ho Pyi , Yong Soo Kim
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L21/28282
摘要： A non-volatile memory device includes a substrate, a tunneling layer over the substrate, a charge trapping layer including a nitride layer and a silicon boron nitride layer over the tunneling layer, and a blocking layer over the charge trapping layer, and a control gate electrode arranged on the blocking layer.
摘要翻译：非易失性存储器件包括衬底，衬底上的隧道层，在隧穿层上方包括氮化物层和氮化硼氮化物层的电荷俘获层，以及电荷俘获层上的阻挡层，以及控制栅极电极布置在阻挡层上。

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