专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5765010A Timing and control circuit and method for a synchronous vector processor 失效
标题翻译：同步矢量处理器的时序控制电路及方法
公开(公告)号：US5765010A
公开(公告)日：1998-06-09
申请号：US421471
申请日：1989-10-13
申请人： Moo-Taek Chung , Jim Childers , Hiroshi Miyaguchi , Manfred Becker
发明人： Moo-Taek Chung , Jim Childers , Hiroshi Miyaguchi , Manfred Becker
IPC分类号： F02B75/02 , G06F15/80 , H04N5/14 , H04N5/775 , H04N9/64 , H04N9/79 , G06F15/00
CPC分类号： G06F15/8092 , H04N5/775 , F02B2075/027 , H04N5/14 , H04N9/641 , H04N9/79
摘要： A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.
摘要翻译：一种用于具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置的定时和控制电路和方法。该电路包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路。

2. 发明授权

US5628025A Timing and control circuit and method for a synchronous vector processor 失效
标题翻译：同步矢量处理器的时序控制电路及方法
公开(公告)号：US5628025A
公开(公告)日：1997-05-06
申请号：US483778
申请日：1995-06-07
申请人： Moo-Taek Chung , Jim Childers , Hiroshi Miyaguchi , Manfred Becker
发明人： Moo-Taek Chung , Jim Childers , Hiroshi Miyaguchi , Manfred Becker
IPC分类号： F02B75/02 , G06F15/80 , H04N5/14 , H04N5/775 , H04N9/64 , H04N9/79 , G06F3/14
CPC分类号： G06F15/8092 , H04N5/775 , F02B2075/027 , H04N5/14 , H04N9/641 , H04N9/79
摘要： A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.
摘要翻译：一种用于具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置的定时和控制电路和方法。该电路包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路。

3. 发明授权

US5210836A Instruction generator architecture for a video signal processor controller 失效
标题翻译：视频信号处理器控制器的指令生成器架构
公开(公告)号：US5210836A
公开(公告)日：1993-05-11
申请号：US421500
申请日：1989-10-13
申请人： Jim Childers , Peter Reinecke , Moo-Taek Chung , Hiroshi Miyaguchi
发明人： Jim Childers , Peter Reinecke , Moo-Taek Chung , Hiroshi Miyaguchi
IPC分类号： F02B75/02 , G06F15/80 , G06T1/20
CPC分类号： G06T1/20 , G06F15/8007 , F02B2075/027
摘要： A synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.
摘要翻译：具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置。处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且能够对视频信号进行实时数字处理。在视频应用中，提供了包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路的数据输入控制电路。

4. 发明授权

US5327541A Global rotation of data in synchronous vector processor 失效
标题翻译：同步矢量处理器中数据的全局旋转
公开(公告)号：US5327541A
公开(公告)日：1994-07-05
申请号：US887228
申请日：1992-05-18
申请人： Peter Reinecke , Jimmie D. Childers , Hiroshi Miyaguchi , Moo-Taek Chung
发明人： Peter Reinecke , Jimmie D. Childers , Hiroshi Miyaguchi , Moo-Taek Chung
IPC分类号： F02B75/02 , G06F15/80 , G06F12/00 , G06F15/76
CPC分类号： G06F15/8092 , G06F15/8015 , F02B2075/027
摘要： An apparatus and method for performing rotation of data in a register file memory. The apparatus utilizes a rotation address generator including rotation value, modulus, and offset registers, a comparator, a data selector, logic circuitry, and a subtractor. A predetermined area (P.times.Q) of the register file memory and a rotation value corresponding to the number of bits to be rotated in the rotation area is designated by an instruction program memory. An instruction decoder signals the register file, modulus register, rotation value register, and offset register of an impending rotation of data, thereby enabling loading of the modulus and rotation value registers and resetting of the offset register. A counter provides a relative address to the comparator and data selector. The comparator compares the relative address with the output of the modulus register, determining whether selected ones of the addressed register file locations fall inside or outside of the rotation area, and send an appropriate signal to the logic circuitry, an OR gate. This OR gate also receives a rotate or not-rotate signal. Consequently, either an absolute address equal to (the value of the relative address-2 * the offset value) mod (8 * the value in the modulus register) or equal to the relative address, based on predetermined conditions, is utilized to access rotationally data from the register file.
摘要翻译：一种用于在寄存器文件存储器中执行数据旋转的装置和方法。该装置使用包括旋转值，模数和偏移寄存器的旋转地址生成器，比较器，数据选择器，逻辑电路和减法器。由指令程序存储器指定寄存器文件存储器的预定区域（PxQ）和与旋转区域中要旋转的位数相对应的旋转值。指令译码器向数据的即将转动的寄存器文件，模数寄存器，旋转值寄存器和偏移寄存器发出信号，从而可以加载模数和旋转值寄存器以及复位偏移寄存器。计数器提供比较器和数据选择器的相对地址。比较器将相对地址与模数寄存器的输出进行比较，确定所寻址的寄存器文件位置中选定的位置是否位于旋转区域的内部或外部，并向OR逻辑电路发送适当的信号。该或门也接收旋转或非旋转信号。因此，利用等于（相对地址-2 *偏移值的值）mod（8 *模数寄存器中的值）或等于相对地址的绝对地址（基于预定条件）被旋转地访问来自寄存器文件的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式