专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08148799B2 Self-aligned bipolar transistor structure 有权
标题翻译：自对准双极晶体管结构
公开(公告)号：US08148799B2
公开(公告)日：2012-04-03
申请号：US12692892
申请日：2010-01-25
申请人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
发明人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
IPC分类号： H01L21/00
CPC分类号： H01L29/0817 , H01L29/66242 , H01L29/7378
摘要： A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.
摘要翻译：双极晶体管结构包括具有第一导电类型的半导体衬底，具有与在形成于半导体衬底的上表面中的隔离电介质材料限定的衬底有源器件区域中形成的第一导电类型相反的第二导电类型的集电极区域包括在集电极区域上形成的具有第一导电类型的本征基极区域和形成在隔离电介质材料上的具有第二导电类型的非本征基极区域的基极区域和具有第二导电性的倾斜的原位掺杂发射极插塞形成在本征基区上。

2. 发明申请

US20100127352A1 SELF-ALIGNED BIPOLAR TRANSISTOR STRUCTURE 有权
标题翻译：自对准双极晶体管结构
公开(公告)号：US20100127352A1
公开(公告)日：2010-05-27
申请号：US12692892
申请日：2010-01-25
申请人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
发明人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
IPC分类号： H01L29/732 , H01L29/73
CPC分类号： H01L29/0817 , H01L29/66242 , H01L29/7378
摘要： A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.
摘要翻译：双极晶体管结构包括具有第一导电类型的半导体衬底，具有与在形成于半导体衬底的上表面中的隔离电介质材料限定的衬底有源器件区域中形成的第一导电类型相反的第二导电类型的集电极区域包括在集电极区域上形成的具有第一导电类型的本征基极区域和形成在隔离电介质材料上的具有第二导电类型的非本征基极区域的基极区域和具有第二导电性的倾斜的原位掺杂发射极插塞形成在本征基区上。

3. 发明授权

US07687887B1 Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter 有权
标题翻译：使用选择性生长的发射极形成自对准双极晶体管结构的方法
公开(公告)号：US07687887B1
公开(公告)日：2010-03-30
申请号：US11607265
申请日：2006-12-01
申请人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
发明人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
IPC分类号： H01L21/00
CPC分类号： H01L29/0817 , H01L29/66242 , H01L29/7378
摘要： A method for forming a self-aligned bipolar transistor structure uses the selective growth of a doped silicon emitter in a sloped oxide emitter window to form the self-aligned structure. In an alternate process flow, the top emitter layer is SiGe with a high Ge content that is etched off selectively after deposition of the extrinsic base layer. In another alternate flow, a nitride plug formed on top of the emitter blocks the extrinsic base implant from the emitter region.
摘要翻译：用于形成自对准双极晶体管结构的方法使用在倾斜的氧化物发射器窗口中的掺杂硅发射体的选择性生长以形成自对准结构。在替代工艺流程中，顶部发射极层是具有高Ge含量的SiGe，其在沉积外部基极层之后被选择性地蚀刻掉。在另一个替代流程中，形成在发射极顶部的氮化物塞从发射极区域阻挡外部基极注入。

4. 发明授权

US08723296B2 Stress compensation for large area gallium nitride or other nitride-based structures on semiconductor substrates 有权
标题翻译：对半导体衬底上的大面积氮化镓或其它基于氮化物的结构的应力补偿
公开(公告)号：US08723296B2
公开(公告)日：2014-05-13
申请号：US12927947
申请日：2010-11-30
申请人： Jamal Ramdani
发明人： Jamal Ramdani
IPC分类号： H01L29/66 , H01L21/20
CPC分类号： H01L21/0254 , H01L21/0237 , H01L21/02458 , H01L21/02639 , H01L29/2003
摘要： A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation.
摘要翻译：一种方法包括在衬底上形成应力补偿堆叠，其中应力补偿堆叠在衬底上具有压应力。该方法还包括在衬底上形成一个或多个III族氮化物岛，其中一个或多个III族氮化物岛在衬底上具有拉伸应力。该方法还包括使用来自应力补偿叠层的压缩应力至少部分地抵消来自一个或多个III族氮化物岛的拉伸应力。形成应力补偿堆叠可以包括在衬底上形成一个或多个氧化物层和一个或多个氮化物层。一个或多个氧化物层可以具有压应力，一个或多个氮化物层可以具有拉伸应力，并且氧化物和氮化物层可以共同地具有压应力。可以选择氧化物层和氮化物层的厚度以提供所需量的应力补偿。

5. 发明申请

US20140077266A1 Heterostructure Transistor with Multiple Gate Dielectric Layers 审中-公开
标题翻译：具有多个栅介质层的异质结晶体晶体管
公开(公告)号：US20140077266A1
公开(公告)日：2014-03-20
申请号：US13617584
申请日：2012-09-14
申请人： Jamal Ramdani , Michael Murphy , Linlin Liu
发明人： Jamal Ramdani , Michael Murphy , Linlin Liu
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/778 , H01L23/3192 , H01L29/2003 , H01L29/42376 , H01L29/513 , H01L29/66431 , H01L29/66462 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A first gate dielectric layer is disposed on the second active layer. A second gate dielectric layer is disposed on the first gate dielectric layer. A passivation layer is disposed over the second gate dielectric layer. A gate extends through the passivation layer to the second gate dielectric layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.
摘要翻译：异质结构半导体器件包括设置在第一有源层上的第一有源层和第二有源层。在第一和第二有源层之间形成二维电子气层。第一栅介质层设置在第二有源层上。第二栅极电介质层设置在第一栅极电介质层上。钝化层设置在第二栅极电介质层上。栅极延伸穿过钝化层到第二栅极介电层。第一和第二欧姆触点电连接到第二有源层。第一和第二欧姆触点横向间隔开，栅极设置在第一和第二欧姆触点之间。

6. 发明授权

US08591427B2 Heart monitoring system or other system for measuring magnetic fields 有权
标题翻译：心脏监测系统或其他用于测量磁场的系统
公开(公告)号：US08591427B2
公开(公告)日：2013-11-26
申请号：US12927204
申请日：2010-11-09
申请人： Lawrence H. Zuckerman , Michael X. Maida , Dennis M. Monticelli , James B. Wieser , Jamal Ramdani , Paul Mawson , Moulay Mohamed Ibourk
发明人： Lawrence H. Zuckerman , Michael X. Maida , Dennis M. Monticelli , James B. Wieser , Jamal Ramdani , Paul Mawson , Moulay Mohamed Ibourk
IPC分类号： A61B5/02
CPC分类号： A61B5/04007 , A61B5/7239 , A61B5/743
摘要： A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart.
摘要翻译：一种系统包括配置成测量第一和第二磁场的至少一个第一磁场传感器。该系统还包括至少一个第二磁场传感器，其配置成基本上不测量第一磁场来测量第二磁场。该系统还包括配置成执行信号消除以产生第一磁场的测量并且基于第一磁场的测量产生输出的处理电路。传感器可以代表磁电传感器。磁电传感器可以被配置为将与第一和/或第二磁场相关联的电信号上变频到更高的频率。处理电路可以被配置为识别与患者心脏相关联的一个或多个问题。

7. 发明授权

US08581579B2 Magneto electric sensor with injected up-conversion or down-conversion 有权
标题翻译：磁电传感器带有上变频或下变频
公开(公告)号：US08581579B2
公开(公告)日：2013-11-12
申请号：US12927205
申请日：2010-11-09
申请人： Lawrence H. Zuckerman , Michael X. Maida , Dennis M. Monticelli , James B. Wieser , Jamal Ramdani
发明人： Lawrence H. Zuckerman , Michael X. Maida , Dennis M. Monticelli , James B. Wieser , Jamal Ramdani
IPC分类号： G01R33/12
CPC分类号： A61B5/04007 , A61B5/7239 , A61B5/743
摘要： A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field. The chopping could involve intermittently shielding the magnetic field sensor from the magnetic field or moving the magnetic field sensor with respect to the magnetic field.
摘要翻译：一种方法包括使用具有交替的磁致伸缩材料层和压电材料的磁场传感器来产生表示磁场的电信号。该方法还包括执行上变频或下变频，使得表示磁场的电信号具有比磁场频率更高或更低的频率。在磁场转换成电信号之前执行上转换或下变频。上转换或下转换可以通过使磁场传感器反复敏感和脱敏来进行。这可以使用永磁体和电磁体，没有永磁体的电磁体或可动永磁体来完成。也可以通过切割磁场来执行上变频或下变频。斩波可能会将磁场传感器与磁场间断地屏蔽或相对于磁场移动磁场传感器。

8. 发明授权

US08377788B2 SiGe heterojunction bipolar transistor and method of forming a SiGe heterojunction bipolar transistor 有权
标题翻译： SiGe异质结双极晶体管和形成SiGe异质结双极晶体管的方法
公开(公告)号：US08377788B2
公开(公告)日：2013-02-19
申请号：US12946305
申请日：2010-11-15
申请人： Wibo Van Noort , Jamal Ramdani , Andre Labonte , Donald Robertson Getchell
发明人： Wibo Van Noort , Jamal Ramdani , Andre Labonte , Donald Robertson Getchell
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/1004 , H01L29/7371
摘要： A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.
摘要翻译：通过蚀刻外延形成的结构来形成SiGe异质结双极晶体管，以形成具有位于其间的集电极区域，帽区域和缺口SiGe基极区域的台面。在SiGe基极区域的凹口中形成保护塞，使得可以在集电区域和盖区域的侧面上形成厚的非导电区域。一旦形成了非导电区域，就去除了保护塞。然后形成外部碱基以位于凹口中并且接触基极区域，随后形成隔离区域和发射极区域。

9. 发明申请

US20110180854A1 Normally-off gallium nitride-based semiconductor devices 有权
标题翻译：通常的氮化镓基半导体器件
公开(公告)号：US20110180854A1
公开(公告)日：2011-07-28
申请号：US12657757
申请日：2010-01-27
申请人： Jamal Ramdani
发明人： Jamal Ramdani
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/225 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.
摘要翻译：一种方法包括在半导体器件中形成松弛层。该方法还包括在松弛层上形成拉伸层，其中拉伸层具有拉伸应力。该方法还包括在松弛层上形成压缩层，其中压缩层具有压应力。压缩层具有大致等于或大于松弛，拉伸和压缩层中的自发极化的压电极化。压缩层中的压电极化可能与压缩层中的自发极化方向相反。松弛层可以包括氮化镓，拉伸层可以包括氮化镓铝，并且压缩层可以包括铝铟镓氮。

10. 发明申请

US20110042778A1 SEMICONDUCTOR DEVICE HAVING LOCALIZED INSULATED BLOCK IN BULK SUBSTRATE AND RELATED METHOD 审中-公开
标题翻译：具有大块基板中的局部绝缘块的半导体器件及相关方法
公开(公告)号：US20110042778A1
公开(公告)日：2011-02-24
申请号：US12917332
申请日：2010-11-01
申请人： Craig Printy , Andre P. Labonte , Jamal Ramdani
发明人： Craig Printy , Andre P. Labonte , Jamal Ramdani
IPC分类号： H01L29/06
CPC分类号： H01L27/1207 , H01L21/76264
摘要： One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate.
摘要翻译：可以在半导体衬底的第一部分周围形成一个或多个沟槽，并且可以在半导体衬底的第一部分之下形成绝缘层。一个或多个沟槽和绝缘层将衬底的第一部分与衬底的第二部分电隔离。可以通过在硅衬底中的诸如硅锗层的衬底中形成掩埋层来形成绝缘层。可以形成通过衬底到掩埋层的一个或多个第一沟槽，并且可以在掩埋层中形成开放空间（例如通过使用对硅上的硅锗的选择性蚀刻）。一个或多个第一沟槽和开放空间可以可选地用绝缘材料填充。可以形成并填充一个或多个第二沟槽以隔离衬底的第一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式