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    • 3. 发明授权
    • Network processor/software control architecture
    • 网络处理器/软件控制架构
    • US06898179B1
    • 2005-05-24
    • US09544896
    • 2000-04-07
    • Brian Mitchell BassJean Louis CalvignacAnthony Matteo GalloMarco C. HeddesMark Anthony RinaldiMichael Steven SiegelColin Beaton VerrilliFabrice Jean Verplanken
    • Brian Mitchell BassJean Louis CalvignacAnthony Matteo GalloMarco C. HeddesMark Anthony RinaldiMichael Steven SiegelColin Beaton VerrilliFabrice Jean Verplanken
    • G06F11/00H04B7/216H04L1/16H04L12/26
    • G06F15/17
    • The transport protocol for communicating between general purpose processors acting as contact points and network processors in a packet processing environment such as Ethernet is provided. In such an environment, there is at least one single control point processor (CP) and a plurality of network processors (NP), sometimes referred to as blades. A typical system could contain two to sixteen network processors, and each network processor connects to a plurality of devices which communicate with each other over a network transport, such as Ethernet. The CP typically controls the functionality and the functioning of the network processors to function in a way that connects one end user with another, whether or not the end user is on the same network processor or a different network processor. There are three types of communication provided; first, there is communication generally referred to as control services and normally there will be only one pico processor which operates as a GCH (guided cell handler) and only one that operates as a guided tree handler (GTH). A path is provided for the controls to the GCH and the GTH commands, and a separate path is provided for the data frames between the GDH's (general data handler) and the CP.
    • 提供了用于在诸如以太网的分组处理环境中用作接触点的通用处理器和网络处理器之间进行通信的传输协议。 在这样的环境中,存在至少一个单个控制点处理器(CP)和多个网络处理器(NP),有时称为刀片。 典型的系统可以包含两到十六个网络处理器,并且每个网络处理器连接到通过诸如以太网的网络传输彼此通信的多个设备。 CP通常控制网络处理器的功能和功能,以使终端用户与另一终端用户相连的方式起作用,无论终端用户是否在同一个网络处理器或不同的网络处理器上。 提供三种通讯方式; 首先,通常被称为控制服务的通信,并且通常将只有一个微微处理器作为GCH(引导的单元处理器)操作,并且只有一个作为引导树处理器(GTH)操作。 为GCH和GTH命令的控制提供路径,并为GDH(通用数据处理程序)和CP之间的数据帧提供单独的路径。
    • 6. 发明授权
    • Mixed queue scheduler
    • 混合队列调度程序
    • US06728253B1
    • 2004-04-27
    • US09405691
    • 1999-09-24
    • Clark Debs JeffriesMarco C. HeddesMark Anthony RinaldiMichael Steven Siegel
    • Clark Debs JeffriesMarco C. HeddesMark Anthony RinaldiMichael Steven Siegel
    • H04L1256
    • H04L47/50H04L2012/5682
    • A method and system are disclosed for allocating data input bandwidth from a source link to a plurality of N data queues each having a variable occupancy value, Qi(t), and a constant decrement rate, Di, where i designated the ith queue among the N queues. First, a threshold occupancy value, T, is designated for the N queues. During each time step of a repeating time interval, &Dgr;t, the occupancy value, Qi, is compared with T. In response to each and every of said N data queues having occupancy values exceeding T, pausing data transmission from the source link to the N data queues, such that overflow within the data queues is minimized. In response to at least one of the N data queues having an occupancy value less than or equal to T, selecting one among the N data queues to be incremented, and incrementing the selected data queue, such that underflow of the selected queue is minimized. In the context of scheduling one cell per time step, the value of T is one. Furthermore, the method of the present invention guarantees that output port occupancy shall never, in that context, exceed two cells.
    • 公开了一种用于将数据输入带宽从源链路分配给多个N个数据队列的方法和系统,每个N个数据队列具有可变占用值Qi(t)和常数递减率Di,其中i指定i < 排队N队列。 首先,为N个队列指定阈值占有率T。 在重复时间间隔的每个时间步长,Deltat,占用值Qi与T进行比较。响应于具有超过T的占用值的所述N个数据队列中的每一个,暂停从源链路到N的数据传输 数据队列,使数据队列中的溢出最小化。 响应于具有小于或等于T的占用值的N个数据队列中的至少一个,选择要增加的N个数据队列中的一个,并增加所选择的数据队列,使得所选队列的下溢最小化。 在每个时间步长调度一个单元格的上下文中,T的值为1。 此外,本发明的方法保证输出端口占用在这方面永远不超过两个小区。
    • 7. 发明授权
    • Lookups by collisionless direct tables and CAMS
    • 通过无碰撞直接表和CAMS查找
    • US08081632B2
    • 2011-12-20
    • US11962558
    • 2007-12-21
    • Gordon Taylor DavisAndreas Guenther HerkersdorfClark Debs JeffriesMark Anthony Rinaldi
    • Gordon Taylor DavisAndreas Guenther HerkersdorfClark Debs JeffriesMark Anthony Rinaldi
    • G06F12/00H04L12/56
    • H04L49/3009H04L45/745H04L45/7453H04L49/351
    • Computers are caused to provide a hash table wherein each entry is associated with a binary key and indexed by a selected portion of a hash value of the associated key, and points to a data structure location for storing non-selected portions of, or the entire hash value of, the binary key, and action data corresponding to the value of the binary key. Content addressable memory entries store a binary key, or a value unique to it, and an association to a corresponding action. Pointers to the data structure use selected portions of binary key hash values as an index when not selected portions of hash values of other binary keys, and associations are established between CAM entry and associated data structure locations when selected portions of the hash values of the binary keys are the same as selected portions of hash values of one or more other binary keys.
    • 导致计算机提供散列表,其中每个条目与二进制密钥相关联并由相关联的密钥的哈希值的选定部分索引,并且指向用于存储未选择的部分或全部的数据结构位置 哈希值,二进制密钥和对应于二进制密钥值的动作数据。 内容可寻址存储器条目存储二进制密钥或其唯一值,以及与相应操作的关联。 指向数据结构的指针使用二进制密钥散列值的选定部分作为索引,当未选择其他二进制密钥的散列值部分时,以及在CAM条目和相关联的数据结构位置之间建立关联时,二进制对象的哈希值的选定部分 键与一个或多个其他二进制键的哈希值的选定部分相同。
    • 8. 发明授权
    • Instruction memory system for multi-processor environment and disjoint tasks
    • 指令存储系统,用于多处理器环境和不相交任务
    • US06760743B1
    • 2004-07-06
    • US09477757
    • 2000-01-04
    • Marco C. HeddesMark Anthony RinaldiBrian Alan Youngman
    • Marco C. HeddesMark Anthony RinaldiBrian Alan Youngman
    • G06F900
    • G06F9/3802G06F9/3851
    • An instruction memory system is shared by a plurality of processors and the system utilizes an increased bandwidth to support the combined number of processors. The total instruction address space is divided into code segments according to the disjoint tasks to be performed. The instruction codes of each processor are consolidated into one copy for control instructions and duplicate copies for other disjoint tasks such as inbound requests and outbound requests that have greater processor contention. Interleaving of the memory arrays for certain disjoint tasks serves to provide a larger number of instructions for these tasks. The system utilizes arbiters to receive all disjoint tasks and to control multiplexors that send addresses to memory arrays.
    • 指令存储器系统由多个处理器共享,并且系统利用增加的带宽来支持组合的处理器数量。 总指令地址空间根据要执行的不相交任务分为代码段。 每个处理器的指令代码被合并到一个副本中,用于控制指令和其他不相交任务的重复副本,例如具有更大处理器争用的入站请求和出站请求。 用于某些不相交任务的存储器阵列的交织用于为这些任务提供更多数量的指令。 该系统利用仲裁器接收所有不相交的任务,并控制向存储器阵列发送地址的多路复用器。