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1. 发明授权

US5296388A Fabrication method for semiconductor devices 失效
标题翻译：半导体器件制造方法
公开(公告)号：US5296388A
公开(公告)日：1994-03-22
申请号：US729490
申请日：1991-07-12
申请人： Shuichi Kameyama , Atsushi Hori , Hiroshi Shimomura , Mizuki Segawa
发明人： Shuichi Kameyama , Atsushi Hori , Hiroshi Shimomura , Mizuki Segawa
IPC分类号： H01L21/20 , H01L21/265 , H01L21/285 , H01L21/331
CPC分类号： H01L29/66272 , H01L21/2022 , H01L21/2652 , H01L21/28525 , Y10S148/011 , Y10S148/124 , Y10S438/969
摘要： A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate. After forming a N-type semiconductor region as the emitter by ion implanting, for instance, as into a P-type semiconductor region as the base, a polysilicon thin film 114 is deposited so as to be implanted with As ions and then heat treated. In this case, an amorphous portion of the N-type semiconductor region and an amorphous silicon thin film in contact therewith are transformed by solid phase epitaxial growth so as to form a single crystal semiconductor region, a single-crystalline silicon thin film, and a polysilicon thin film, thus forming a bipolar element having an emitter.
摘要翻译：连接多晶半导体薄膜和包含在单晶半导体衬底中形成的高浓度杂质的半导体区域的半导体器件的制造方法。在通过离子注入形成作为发射极的N型半导体区域之后，例如作为基底的P型半导体区域，沉积多晶硅薄膜114，以便注入As离子，然后进行热处理。在这种情况下，通过固相外延生长来转变N型半导体区域的非晶部分和与其接触的非晶硅薄膜，从而形成单晶半导体区域，单晶硅薄膜和多晶硅薄膜，从而形成具有发射极的双极元件。

2. 发明授权

US5254485A Method for manufacturing bipolar semiconductor device 失效
标题翻译：制造双极型半导体器件的方法
公开(公告)号：US5254485A
公开(公告)日：1993-10-19
申请号：US760987
申请日：1991-09-17
申请人： Mizuki Segawa , Shuichi Kameyama , Hiroshi Shimomura , Atsushi Hori
发明人： Mizuki Segawa , Shuichi Kameyama , Hiroshi Shimomura , Atsushi Hori
IPC分类号： H01L21/331 , H01L21/265 , H01L29/70
CPC分类号： H01L29/66272 , Y10S148/01
摘要： There is disclosed a method for manufacturing a bipolar semiconductor device in which emitter region and active base region are formed by implanting impurities of first and second conduction types in a first semiconductor region of the first conduction type to be a collector through a non-single crystalline semiconductor thin film, a second semiconductor thin film is formed on the first semiconductor thin film, and an impurity of the first conduction type is introduced in the second semiconductor thin film after patterning the first and second semiconductor thin film so as to form an emitter electrode.
摘要翻译：公开了一种制造双极型半导体器件的方法，其中通过将第一和第二导电类型的杂质注入第一导电类型的第一半导体区域中作为集电极的非单晶结构形成发射极区域和有源基极区域在第一半导体薄膜上形成第二半导体薄膜，在对第一和第二半导体薄膜进行图案化之后，将第一导电类型的杂质引入到第二半导体薄膜中，以形成发射极。

3. 发明授权

US5202277A Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5202277A
公开(公告)日：1993-04-13
申请号：US918933
申请日：1992-07-22
申请人： Shuichi Kameyama , Atsushi Hori , Hiroshi Shimomura , Mizuki Segawa
发明人： Shuichi Kameyama , Atsushi Hori , Hiroshi Shimomura , Mizuki Segawa
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28114
摘要： A method of fabricating a semiconductor device having gate-drain overlap MOSFETs in which side surfaces of upper portions of gate lines are anisotropically etched using a buffer film as an etch stop is disclosed. An insulating film as a gate insulator is formed on a semiconductor layer of a first conductivity type. A first conductive film is formed on the gate insulator. A buffer film having openings in gate line regions is formed on the first conductive film. A second conductive film is formed on the buffer film. The second conductive film is patterned into wiring shape to form upper portions of gate lines covering the openings of the buffer film. Ions of a second conductivity type are implanted into the semiconductor layer using the upper portions of the gate lines as an implant mask to form sources and drains in the semiconductor layer. Sidewall spacers are formed on the sides of the upper portions of the gate lines. The buffer film and the first conductive film are etched using the upper portions of the gate lines and the sidewall spacers as an etching mask to form under portions of the gate lines.
摘要翻译：公开了一种制造具有栅极 - 漏极重叠MOSFET的半导体器件的方法，其中栅极线的上部的侧表面使用缓冲膜作为蚀刻停止点进行各向异性蚀刻。作为栅极绝缘体的绝缘膜形成在第一导电类型的半导体层上。在栅极绝缘体上形成第一导电膜。在第一导电膜上形成在栅线区域具有开口的缓冲膜。在缓冲膜上形成第二导电膜。将第二导电膜图案化成布线形状，以形成覆盖缓冲膜的开口的栅极线的上部。使用栅极线的上部作为注入掩模将第二导电类型的离子注入到半导体层中，以在半导体层中形成源极和漏极。侧壁间隔件形成在栅极线的上部的侧面上。使用栅极线和侧壁间隔物的上部作为蚀刻掩模蚀刻缓冲膜和第一导电膜，以在栅极线的一部分形成。

4. 发明授权

US5320974A Method for making semiconductor transistor device by implanting punch through stoppers 失效
标题翻译：通过将止动器植入穿孔来制造半导体晶体管器件的方法
公开(公告)号：US5320974A
公开(公告)日：1994-06-14
申请号：US31761
申请日：1993-03-15
申请人： Atsushi Hori , Mizuki Segawa , Hiroshi Shimomura , Shuichi Kameyama
发明人： Atsushi Hori , Mizuki Segawa , Hiroshi Shimomura , Shuichi Kameyama
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L21/266
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/665
摘要： Insulating films formed on side walls of a gate electrode are removed for a self-alignment to selectively implant impurities only into end portions of a source region and a drain region. Therefore, p.sup.+ -type semiconductor regions are selectively formed only on sides near a channel region of the source and the drain regions. A punch through of the source or drain region is prevented by the p.sup.+ -type semiconductor regions controlling an inversion threshold voltage. Therefore, the impurity concentration of the p-type substrate can be settled low, and the semiconductor transistor device can be miniaturized without increasing a parasitic junction capacitance. Moreover, since the impurity concentration in the channel region is ununiform, a drivability of the transistor can be increased. As a result, a semiconductor transistor device with a high withstand voltage and a high drivability in which the inversion threshold voltage can be easily controlled, and a method for producing the same are provided.
摘要翻译：去除形成在栅电极的侧壁上的绝缘膜以进行自对准以选择性地将杂质仅仅植入源极区域和漏极区域的端部。因此，仅在源极和漏极区的沟道区域附近的侧面选择性地形成p +型半导体区域。通过控制反转阈值电压的p +型半导体区域防止源区或漏区的穿通。因此，p型衬底的杂质浓度可以很低，并且半导体晶体管器件可以小型化而不增加寄生结电容。此外，由于沟道区域中的杂质浓度不均匀，所以可以提高晶体管的驱动能力。结果，提供了具有高耐受电压和高驱动能力的半导体晶体管器件，其中可以容易地控制反转阈值电压及其制造方法。

5. 发明授权

US5158903A Method for producing a field-effect type semiconductor device 失效
标题翻译：场效应型半导体器件的制造方法
公开(公告)号：US5158903A
公开(公告)日：1992-10-27
申请号：US606493
申请日：1990-10-31
申请人： Atsushi Hori , Shuichi Kameyama , Hiroshi Shimomura , Mizuki Segawa
发明人： Atsushi Hori , Shuichi Kameyama , Hiroshi Shimomura , Mizuki Segawa
IPC分类号： H01L29/78 , H01L21/265 , H01L21/266 , H01L21/336
CPC分类号： H01L29/66575 , H01L21/26586 , H01L21/266 , H01L29/6659
摘要： A method for producing field-effect type semiconductor devices is disclosed which includes the steps of: forming a gate insulator film on a semiconductor substrate; forming a conductor film on the gate insulator film; and implanting impurity ions in the semiconductor substrate through the gate insulator film and the conductor film for the purpose of controlling a threshold voltage of the device, wherein the conductor film is employed as a gate electrode of the device. The method of this invention has the excellent advantages of readily controlling a threshold voltage of field-effect type semiconductor devices and of preventing the scatter of the threshold voltage values. An alternative embodiment employs formation of a second conductor film and implantation from an inclined direction.
摘要翻译：公开了一种用于制造场效半导体器件的方法，其包括以下步骤：在半导体衬底上形成栅极绝缘膜; 在栅极绝缘膜上形成导体膜; 以及通过栅极绝缘膜和导体膜将杂质离子注入到半导体衬底中，以便控制器件的阈值电压，其中导体膜用作器件的栅电极。本发明的方法具有容易控制场效半导体器件的阈值电压和防止阈值电压值散射的优点。替代实施例采用形成第二导体膜并从倾斜方向注入。

6. 发明授权

US5756382A Manufacturing method of CMOS transistor 失效
标题翻译： CMOS晶体管的制造方法
公开(公告)号：US5756382A
公开(公告)日：1998-05-26
申请号：US784354
申请日：1997-01-23
申请人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
发明人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/823814 , Y10S148/147
摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

7. 发明授权

US5726071A Manufacturing method of CMOS transistor 失效
标题翻译： CMOS晶体管的制造方法
公开(公告)号：US5726071A
公开(公告)日：1998-03-10
申请号：US789315
申请日：1997-01-23
申请人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
发明人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
IPC分类号： H01L21/8238 , H01L21/70
CPC分类号： H01L21/823814 , Y10S148/147
摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。在比第一热处理的温度低的温度下对N型重掺杂扩散层进行第二次热处理。使用P沟道晶体管的栅电极作为掩模来形成作为P沟道晶体管的源极或漏极的P型重掺杂扩散层。然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

8. 发明授权

US5686340A Manufacturing method of CMOS transistor 失效
标题翻译： CMOS晶体管的制造方法
公开(公告)号：US5686340A
公开(公告)日：1997-11-11
申请号：US723710
申请日：1996-09-30
申请人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
发明人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/823814 , Y10S148/147
摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。在比第一热处理的温度低的温度下对N型重掺杂扩散层进行第二次热处理。使用P沟道晶体管的栅电极作为掩模来形成作为P沟道晶体管的源极或漏极的P型重掺杂扩散层。然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

9. 发明授权

US5409847A Manufacturing method of CMOS transistor in which heat treatment at higher temperature is done prior to heat treatment at low temperature 失效
标题翻译：在低温下进行热处理之前，在较高温度下进行热处理的CMOS晶体管的制造方法
公开(公告)号：US5409847A
公开(公告)日：1995-04-25
申请号：US141727
申请日：1993-10-27
申请人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
发明人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/823814 , Y10S148/147
摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

10. 发明授权

US5618748A Manufacturing method of CMOS transistor with no reduction of punch-through voltage 失效
标题翻译：没有降低穿通电压的CMOS晶体管的制造方法
公开(公告)号：US5618748A
公开(公告)日：1997-04-08
申请号：US443266
申请日：1995-05-17
申请人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
发明人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
IPC分类号： H01L21/8238 , H01L21/70
CPC分类号： H01L21/823814 , Y10S148/147
摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

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