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1. 发明授权

US5719446A Multilayer interconnect structure for semiconductor device and method of manufacturing same 失效
标题翻译：用于半导体器件的多层互连结构及其制造方法
公开(公告)号：US5719446A
公开(公告)日：1998-02-17
申请号：US797925
申请日：1997-02-12
申请人： Mitsuru Taguchi , Keiichi Maeda , Hiroshi Suzawa , Hidenori Kenmotsu , Teruo Hirayama
发明人： Mitsuru Taguchi , Keiichi Maeda , Hiroshi Suzawa , Hidenori Kenmotsu , Teruo Hirayama
IPC分类号： H01L21/203 , H01L21/205 , H01L21/3205 , H01L21/324 , H01L21/768 , H01L23/12 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/41
CPC分类号： H01L23/5226 , H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： A multilayer interconnect structure for a semiconductor device. The structure comprises a lower patterned metallization layer, a higher patterned metallization layer, and filled holes for electrically interconnecting these two layers. The two metallization layers are formed out of aluminum or an aluminum alloy by high-temperature aluminum sputtering or aluminum reflow techniques. A suction-preventing layer is formed either at the bottoms of the contact holes or on the surface of the lower metallization layer to prevent the material of the lower metallization layer from being sucked into the overlying contact holes.
摘要翻译：一种用于半导体器件的多层互连结构。该结构包括下图案化的金属化层，较高图案化的金属化层和用于电连接这两层的填充孔。两个金属化层由铝或铝合金通过高温铝溅射或铝回流技术形成。在接触孔的底部或下部金属化层的表面上形成防吸水层，以防止下部金属化层的材料被吸入上覆的接触孔中。

2. 发明授权

US06750606B2 Gate-to-electrode connection in a flat panel display 失效
标题翻译：平板显示器中的栅极与电极的连接
公开(公告)号：US06750606B2
公开(公告)日：2004-06-15
申请号：US09947288
申请日：2001-09-05
申请人： Hidenori Kenmotsu
发明人： Hidenori Kenmotsu
IPC分类号： H01J1924
CPC分类号： H01J9/261 , H01J9/025 , H01J31/127
摘要： A flat panel display and manufacturing method therefor is provided having a baseplate hermetically sealed to a faceplate. A first electrode and a resistive layer are formed on the baseplate. An insulating layer is deposited on the resistive layer. A second electrode is formed over the insulating layer. A passivation layer is deposited over the insulating layer and a gate is formed over the passivation layer. Openings are concurrently formed in the gate and insulation layer and used to form an emitter cavity. A conductive glue is deposited to form a gate-to-electrode contact for connecting the gate and the second electrode. An emitter is formed in the emitter cavity and emitter material outside of the emitter cavity is removed.
摘要翻译：提供了一种具有密封到面板的底板的平板显示器及其制造方法。第一电极和电阻层形成在基板上。绝缘层沉积在电阻层上。第二电极形成在绝缘层上。钝化层沉积在绝缘层之上，并且在钝化层上形成栅极。开口同时形成在栅极和绝缘层中，并用于形成发射器腔。沉积导电胶以形成用于连接栅极和第二电极的栅极 - 电极接触。在发射器腔中形成发射极，去除发射极腔外部的发射极材料。

3. 发明授权

US5399530A Method of forming interconnection structure to prevent outgassing 失效
标题翻译：形成互连结构以防止排气的方法
公开(公告)号：US5399530A
公开(公告)日：1995-03-21
申请号：US78103
申请日：1993-06-18
申请人： Hidenori Kenmotsu
发明人： Hidenori Kenmotsu
IPC分类号： H01L21/28 , H01L21/283 , H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76843 , H01L21/76877
摘要： The disclosure relates to a method of forming an interconnection structure. In the method, firstly, a SOG layer is deposited on a first aluminum conductive layer which is formed on a substrate. Then, a through-hole is formed by opening the SOG layer so as to expose two opposed surfaces of the SOG layer and an upper surface of the first conductive layer. Then, the substrate, the first conductive layer and the SOG layer are heated at a first temperature ranging from 450.degree. to 550.degree. C. Then, a titanium layer is formed on the through-hole so as to mask the two opposed surfaces of the SOG layer. Then, a second aluminum conductive layer is deposited on the SOG layer by sputtering so as to fill the through-hole with the second conductive layer. During the sputtering of the second conductive layer, the release of water vapor from the SOG layer is suppressed, thereby obtaining an interconnection structure having a good contact.
摘要翻译：本公开涉及形成互连结构的方法。在该方法中，首先，在形成在基板上的第一铝导电层上沉积SOG层。然后，通过打开SOG层形成通孔，以暴露SOG层的两个相对表面和第一导电层的上表面。然后，在450℃〜550℃的第一温度下对基板，第一导电层和SOG层进行加热。然后，在通孔上形成钛层，以掩蔽 SOG层。然后，通过溅射在SOG层上沉积第二铝导电层，以便用第二导电层填充通孔。在溅射第二导电层期间，抑制了从SOG层的水蒸汽的释放，从而获得具有良好接触的互连结构。

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