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    • 4. 发明授权
    • Semiconductor device having input protection circuit
    • 具有输入保护电路的半导体器件
    • US5949109A
    • 1999-09-07
    • US790804
    • 1997-01-30
    • Mitsuru ShimizuSyuso FujiiKenji NumataMasaharu Wada
    • Mitsuru ShimizuSyuso FujiiKenji NumataMasaharu Wada
    • H01L27/02H01L23/62
    • H01L27/0251
    • According to this invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.
    • 根据本发明,在半导体衬底上形成阱区。 在阱区中形成n +型第一半导体区,并且用于接收外部信号的输入焊盘连接在第一半导体区附近。 该输入焊盘连接到由逆变器电路构成的集成电路的输入电路和用于接收外部信号的外部端子。 在位于第一半导体区域的两侧的阱区中形成N +型第二半导体区域。 对这些第二半导体区域施加接地电位Vss。 在阱区中围绕这些第二半导体区域形成p +型第三半导体区域。 接地电位施加到第三半导体区域。 因此,在输入焊盘和接地电位之间形成由寄生晶体管和寄生二极管形成的并联电路。 寄生晶体管在静电放电时导通,当向输入焊盘施加用于测试的负电位时,寄生二极管导通,从而防止布置在半导体衬底上的晶体管的错误操作。
    • 6. 发明授权
    • Instant camera
    • 即时相机
    • US5794077A
    • 1998-08-11
    • US740392
    • 1996-10-29
    • Mitsuru ShimizuKo AosakiMichio Cho
    • Mitsuru ShimizuKo AosakiMichio Cho
    • G03B17/52G03B17/50
    • G03B17/52G03B2219/045
    • A single-use instant camera includes a main body, having the taking lens and the shutter mechanism. A film unit containing chamber is formed in the main body, and contains a plurality of instant the film units stacked on one another. The containing chamber is opened toward a rear and has a front wall. An exposure aperture is formed in the front wall, and receives the image-recording portion of the film units, to provide the film units with exposure to light a entered through the taking lens from an object to be photographed. A front cover is disposed in front of the main body to cover the main body. An advancing claw mechanism is disposed between the front cover and the main body, and advances an exposed one of the film units to be exited. A flash device is disposed between the front cover and the main body, and applies illuminating light to the object. A back lid is disposed behind the containing chamber, is engaged with the main body, and closes the containing chamber. A pressure plate is mounted on the back lid, and presses the film units toward the exposure aperture.
    • 一次性即时照相机包括具有拍摄镜头和快门机构的主体。 在主体中形成有胶片单元容纳室,并且包含彼此堆叠的多个即时胶片单元。 容纳室朝向后方开口并具有前壁。 在前壁中形成曝光孔,并且接收胶片单元的图像记录部分,以便从被拍摄物体向胶片单元提供通过拍摄镜头进入的光的曝光。 前盖设置在主体的前面以覆盖主体。 前进爪机构设置在前盖和主体之间,并且使被退出的一个胶片单元前进。 闪光装置设置在前盖和主体之间,并且向对象施加照明光。 后盖设置在容纳室的后面,与主体接合并且封闭容纳室。 压板安装在后盖上,并将胶片单元压向曝光孔。
    • 8. 发明授权
    • Input protection circuit for semiconductor integrated circuit device
    • 半导体集成电路器件的输入保护电路
    • US4994874A
    • 1991-02-19
    • US425950
    • 1989-10-24
    • Mitsuru ShimizuYoshio OkadaSyuso FujiiShozo Saito
    • Mitsuru ShimizuYoshio OkadaSyuso FujiiShozo Saito
    • H01L27/04H01L21/822H01L23/60H01L27/02
    • H01L27/0259
    • First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad. The first impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the first and third impurity regions constitute a first bipolar transistor for input protection and the second impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the second and third impurity regions constitute a second bipolar transistor for input protection. The resistor and the first and second bipolar transistors constitute an input protection circuit.
    • 在N型半导体衬底中形成的P型半导体衬底或P阱区域的表面区域中,第一至第三N +型杂质区彼此分开地预定距离地形成。 第一杂质区域连接到电源,第二杂质区域连接到接地端子。 形成在第一和第二杂质区域之间的第三杂质区域连接到另一端连接到信号输入焊盘的输入保护电阻器的一端。 位于第一和第三杂质区域之间的第一杂质区域,第三杂质区域和P型半导体衬底或P阱区域的部分构成用于输入保护的第一双极晶体管,第二杂质区域,第三杂质区域 位于第二和第三杂质区之间的P型半导体衬底或P阱区的部分构成用于输入保护的第二双极晶体管。 电阻器和第一和第二双极晶体管构成输入保护电路。