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1. 发明授权

US4660181A Memory system 失效
标题翻译：内存系统
公开(公告)号：US4660181A
公开(公告)日：1987-04-21
申请号：US714396
申请日：1985-03-21
申请人： Mitsuo Saito , Takeshi Aikawa , Akio Mori
发明人： Mitsuo Saito , Takeshi Aikawa , Akio Mori
IPC分类号： G06F3/153 , G06F12/04 , G09G5/00 , G09G5/39 , G09G5/395 , G11C7/00 , G11C7/10 , G11C8/00 , G11C8/12
CPC分类号： G11C8/00 , G06F12/04 , G11C7/00 , G11C7/1006 , G11C8/12
摘要： A memory system includes a memory which consists of a plurality of bit memory cells each capable of being independently accessible and of storing bit data in at least a first and a second different predetermined bit width access mode. A multiplexer and address decoder are provided together with a bit width register for producing first and second write control signals corresponding to the first and second access modes respectively for enabling writing within the independently accessible memory cells of data having respectively first and a different second bit width.
摘要翻译：存储器系统包括存储器，该存储器由多个位存储器单元构成，每个存储器单元能独立存取，并且以至少第一和第二不同的预定位宽度访问模式存储位数据。多路复用器和地址解码器与位宽寄存器一起提供，用于产生分别对应于第一和第二访问模式的第一和第二写入控制信号，以使得能够在可独立存取的存储单元内写入分别具有第一和不同的第二位宽的数据。

2. 发明授权

US4959871A Image input/output apparatus 失效
标题翻译：图像输入/输出设备
公开(公告)号：US4959871A
公开(公告)日：1990-09-25
申请号：US244595
申请日：1988-09-13
申请人： Akio Mori , Takeshi Aikawa , Mitsuo Saito
发明人： Akio Mori , Takeshi Aikawa , Mitsuo Saito
IPC分类号： B41J3/28 , B41J2/32 , B41J3/36
CPC分类号： B41J2/32 , B41J3/36
摘要： A manually movable input/output peripheral device is provided which includes an input/output head or transducer which is manually movable by the user, a guide member which controls the direction of movement of the transducer, and distance measuring device. Data transfer between the transducer and a recording surface is controlled at a rate dependent on the speed which the transducer is moved across the recording surface. Thus, the device is insensitive to variations in operating speed.
摘要翻译：提供了一种可手动移动的输入/输出外围设备，其包括可由用户手动移动的输入/输出头或换能器，控制换能器的移动方向的导向构件和距离测量装置。换能器和记录表面之间的数据传输以取决于换能器在记录表面上移动的速度的速率被控制。因此，设备对操作速度的变化不敏感。

3. 发明授权

US4688032A Image display control apparatus 失效
标题翻译：图像显示控制装置
公开(公告)号：US4688032A
公开(公告)日：1987-08-18
申请号：US879539
申请日：1986-06-24
申请人： Mitsuo Saito , Takeshi Aikawa , Akio Mori
发明人： Mitsuo Saito , Takeshi Aikawa , Akio Mori
IPC分类号： G09G1/02 , G09G5/39 , G09G1/16
CPC分类号： G09G5/39
摘要： Document image data stored in an image memory with a large memory capacity capable of storing larger data than the number of picture elements of a display unit is accessed and read out by using a mapping memory which stores the address data to specify the memory locations of picture element data groups in the image memory. The document image data read out are edited, and then are seen as document images by the display unit.
摘要翻译：存储在具有能够存储比显示单元的图像元素数量更大的数据的大存储容量的图像存储器中的文档图像数据通过使用存储地址数据以指定图像的存储器位置的映射存储器被读取和读出图像存储器中的元素数据组。读出的文件图像数据被编辑，然后被显示单元看作是文档图像。

4. 发明授权

US5561774A Parallel processing type processor system with trap and stall control functions 失效
标题翻译：并行处理型处理器系统具有陷波和失速控制功能
公开(公告)号：US5561774A
公开(公告)日：1996-10-01
申请号：US291582
申请日：1994-08-16
申请人： Takeshi Aikawa , Mitsuo Saito , Kenji Minagawa , Kenji Takeda
发明人： Takeshi Aikawa , Mitsuo Saito , Kenji Minagawa , Kenji Takeda
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3863 , G06F9/3885
摘要： A parallel processing type processor system with trap and stall control functions capable of operating without increasing the cycle time, such that the lowering of the clock frequency in the system can be prevented. In the system, the processor units are controlled such that when an exception is caused in an execution of at least one of the instructions supplied to the processor units concurrently, the processings of all of the instructions supplied to the processor units concurrently are aborted. In addition, the processings of the instructions supplied to the processor units concurrently are stalled when it is not possible to deny a possibility for an occurrence of an exception in the execution of the instructions supplied to the processor units concurrently.
摘要翻译：一种具有陷波和失速控制功能的并行处理型处理器系统，其能够在不增加周期时间的情况下进行操作，从而可以防止系统中的时钟频率的降低。在该系统中，处理器单元被控制，使得当在执行提供给处理器单元的至少一个指令的同时执行异常时，同时提供给处理器单元的所有指令的处理被中止。此外，当不可能在执行提供给处理器单元的指令的同时拒绝发生异常的可能性时，同时提供给处理器单元的指令的处理被停止。

5. 发明授权

US5414822A Method and apparatus for branch prediction using branch prediction table with improved branch prediction effectiveness 失效
标题翻译：使用具有改进的分支预测有效性的分支预测表进行分支预测的方法和装置
公开(公告)号：US5414822A
公开(公告)日：1995-05-09
申请号：US863181
申请日：1992-04-03
申请人： Mitsuo Saito , Takeshi Aikawa , Junji Mori
发明人： Mitsuo Saito , Takeshi Aikawa , Junji Mori
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3806 , G06F9/3844
摘要： The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch prediction uses a branch prediction table for registering entries, each entry including a branching address, a branch target address, and an instruction position indicating a position of the predicted branch instruction in group of instructions to be executed concurrently, or an entry address indicating a position of each entry in the associative memory of the table. A correctness of the predicted branch instruction is checked by using actual branch target address and/or actual instruction position of actual branch instruction encountered in the actual execution of presently fetched instructions. When the predicted branch instruction is incorrect, instructions fetched at a next processing timing are invalidated and the entry in the table is rewritten.
摘要翻译：该分支预测使用由适用于超标量处理器的关联存储器形成的分支预测表，而不会导致分支预测中的混淆。分支预测使用用于登记条目的分支预测表，每个条目包括分支地址，分支目标地址和指示同时执行的指令组中的预测分支指令的位置的指示位置，或指示每个条目在表的关联记忆中的位置。通过使用实际分支目标地址和/或在当前取得的指令的实际执行中遇到的实际分支指令的实际指令位置来检查预测分支指令的正确性。当预测分支指令不正确时，在下一个处理定时取出的指令无效，表中的条目被重写。

6. 发明授权

US5163127A Three dimensional graphic processing apparatus 失效
标题翻译：三维图形处理装置
公开(公告)号：US5163127A
公开(公告)日：1992-11-10
申请号：US687772
申请日：1991-04-19
申请人： Nobuyuki Ikumi , Mitsuo Saito , Takeshi Aikawa , Masahide Ohhashi
发明人： Nobuyuki Ikumi , Mitsuo Saito , Takeshi Aikawa , Masahide Ohhashi
IPC分类号： G06T15/40 , G06T15/80
CPC分类号： G06T15/87
摘要： A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.
摘要翻译：三维图形处理装置包括用于对三角形多边形的每条扫描线进行线性插值计算的n个运算IC（集成电路），以获得像素的强度值和深度坐标值，以及用于存储计算结果的两种类型的n个存储器。在一个处理周期中，n个运算IC并行地执行在单个三角形多边形的单个扫描线上连续的n个不同像素的线性插值计算。每个算术IC在一个处理周期中为每n个像素计算每个运算IC，并且相应的一个存储器存储计算结果。

7. 发明授权

US4992977A Cache memory device constituting a memory device used in a computer 失效
标题翻译：构成计算机中使用的存储装置的高速缓存存储装置
公开(公告)号：US4992977A
公开(公告)日：1991-02-12
申请号：US173296
申请日：1988-03-25
申请人： Tsukasa Matoba , Takeshi Aikawa , Ken-ichi Maeda , Mitsuo Saito , Mitsuyoshi Okamura
发明人： Tsukasa Matoba , Takeshi Aikawa , Ken-ichi Maeda , Mitsuo Saito , Mitsuyoshi Okamura
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0848
摘要： A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.
摘要翻译：高速缓冲存储器装置包括数据高速缓存存储器，指令高速缓存存储器，指令代码区域改变检测器和指令代码改变处理器。指令代码区域改变检测器决定处理器对数据高速缓冲存储器的写入写入是到数据区还是主存储器的指令区。当写入访问指令区时，指令代码变更处理器通过数据高速缓冲存储器来执行直接写入主存储器，并且当处理器地址的数据被缓存在指令高速缓存存储器的标签部分中时，使标签部分的有效标志。

8. 发明授权

US5377339A Computer for simultaneously executing instructions temporarily stored in a cache memory with a corresponding decision result 失效
标题翻译：用于同时执行临时存储在具有相应决定结果的高速缓冲存储器中的指令的计算机
公开(公告)号：US5377339A
公开(公告)日：1994-12-27
申请号：US191069
申请日：1994-02-03
申请人： Mitsuo Saito , Kenji Minagawa , Takeshi Aikawa
发明人： Mitsuo Saito , Kenji Minagawa , Takeshi Aikawa
IPC分类号： G06F9/38 , G06F12/08 , G06F15/16 , G06F9/00
CPC分类号： G06F9/382 , G06F9/3808 , G06F9/3838 , G06F9/3853 , G06F9/3885
摘要： A computer for simultaneously executing plural instructions decides the kind of operation and the possibility of simultaneous execution for the plural instructions as the instructions are read out from a main memory to a cache memory. The plural instructions and a corresponding decision result are stored in the cache memory. The decision process is performed for several groups of the plural instructions read out from the main memory to the cache memory in order. Then, the plural instructions are respectively assigned to a corresponding operation unit according to the decision result, and are subsequently executed by the corresponding operation unit. As a result of this arrangement, the repeated decision process for the plural instructions is not necessary when they are later read out from the cache memory to the operation unit.
摘要翻译：当从主存储器向高速缓冲存储器读出指令时，用于同时执行多个指令的计算机决定多种指令的操作种类和同时执行的可能性。多个指令和相应的判定结果存储在高速缓冲存储器中。对从主存储器读出的多组指令的顺序执行到高速缓冲存储器的决定处理。然后，根据判定结果将多个指令分别分配给对应的运算单元，并由随后的运算单元执行。作为这种布置的结果，当它们稍后从高速缓冲存储器读出到操作单元时，不需要多个指令的重复确定处理。

9. 发明授权

US5446849A Electronic computer which executes squash branching 失效
标题翻译：执行南瓜分支的电子计算机
公开(公告)号：US5446849A
公开(公告)日：1995-08-29
申请号：US799981
申请日：1991-11-29
申请人： Kenji Minagawa , Takeshi Aikawa , Mitsuo Saito
发明人： Kenji Minagawa , Takeshi Aikawa , Mitsuo Saito
IPC分类号： G06F9/38 , G06F12/10
CPC分类号： G06F12/1063 , G06F9/30072 , G06F9/3842 , G06F9/3859 , G06F12/1027
摘要： An electronic computer according to this invention is capable of executing a plurality of instructions simultaneously. It is characterized by comprising a flag adding section for judging whether or not each of a plurality of instruction is either a delayed branch instruction or a squash branch instruction, and based on the results, adding a flag indicating an abort condition to each instruction, and a command execute abort section for aborting execution of each instruction on the basis of whether or not the flag added to each instruction to indicate the abort condition and each branch instruction hold true.
摘要翻译：根据本发明的电子计算机能够同时执行多个指令。其特征在于包括标志添加部分，用于判断多个指令中的每一个是延迟分支指令还是南瓜分支指令，并且基于该结果，向每个指令添加指示中止条件的标志，以及一个命令执行中止部分，用于根据添加到每个指令的标志是否指示中止条件和每个分支指令成立，中止每个指令的执行。

10. 发明授权

US4945510A Register device 失效
标题翻译：注册设备
公开(公告)号：US4945510A
公开(公告)日：1990-07-31
申请号：US133737
申请日：1987-12-16
申请人： Ken-ichi Maeda , Mitsuo Saito , Takeshi Aikawa , Tsukasa Matoba , Mitsuyoshi Okamura
发明人： Ken-ichi Maeda , Mitsuo Saito , Takeshi Aikawa , Tsukasa Matoba , Mitsuyoshi Okamura
IPC分类号： G06F9/34 , G06F9/42 , G06F9/46
CPC分类号： G06F9/30116 , G06F9/4426 , G06F9/462
摘要： A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching control unit in response to a write instruction. A write flag representing whether data is written in each of the registers is held by the write flag memory unit. The read control unit determines, in response to a read instruction, a register in which data is written most recently of a plurality of registers corresponding to each other between the register sets with reference to the write flags, thereby reading out data from the register.

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