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1. 发明专利

JP2005302121A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2005302121A
公开(公告)日：2005-10-27
申请号：JP2004115427
申请日：2004-04-09
申请人： Mitsubishi Heavy Ind Ltd , Seiko Epson Corp , セイコーエプソン株式会社 , 三菱重工業株式会社
发明人： TAGUCHI KAZUO , ISHII SHIGERU , KURODA YOSHIKATSU , TAKAHASHI DAISUKE
IPC分类号： G11C11/41 , H01L21/8244 , H01L27/11 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of guaranteeing a fast operation while increasing soft error resistance.
SOLUTION: This semiconductor memory device includes an SRAM memory cell formed on an SOI substrate. Inverters INV1 and INV2 include p type load transistors TP1 and TP2 whose sources are connected to a high potential power supply line VDD, n type driving transistors TN1 and TN2 whose sources are connected to a low potential power supply line VSS, and n type resistance added transistors TD1 and TD2 whose sources and drains are connected between storage nodes N1 and N2 and driving transistors TN1 and TN2 and whose gates are connected to a word line WL. In each of the resistance added transistors TD1 and TD2, a conductive state is set between the source and the drain when a gate voltage is the power supply voltage Vss of a low potential side.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够在增加软错误阻力的同时保证快速操作的半导体存储器件。解决方案：该半导体存储器件包括形成在SOI衬底上的SRAM存储单元。反相器INV1和INV2包括其源极连接到高电位电源线VDD的p型负载晶体管TP1和TP2，源极连接到低电位电源线VSS的n型驱动晶体管TN1和TN2，以及n型电阻相加其源极和漏极连接在存储节点N1和N2与驱动晶体管TN1和TN2之间并且其栅极连接到字线WL的晶体管TD1和TD2。在每个电阻加法晶体管TD1和TD2中，当栅极电压是低电位侧的电源电压Vss时，在源极和漏极之间设置导通状态。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2010183087A Semiconductor circuit 有权
标题翻译：半导体电路
公开(公告)号：JP2010183087A
公开(公告)日：2010-08-19
申请号：JP2010036192
申请日：2010-02-22
申请人： Mitsubishi Heavy Ind Ltd , 三菱重工業株式会社
发明人： ISHII SHIGERU , YAMAMOTO KENSUKE , TAKAHASHI DAISUKE
IPC分类号： H01L21/822 , G11C11/417 , H01L21/8238 , H01L21/8242 , H01L27/04 , H01L27/08 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/786 , H03K19/096 , H03K19/20
摘要： PROBLEM TO BE SOLVED: To improve the reliability of an electronic apparatus loaded with a semiconductor circuit by achieving the semiconductor circuit having excellent radiation resistance characteristics. SOLUTION: The semiconductor circuit includes: a first circuit block 1 in which a plurality of pMOS transistors 11 are connected in series or connected to a parallel circuit provided with one pMOS transistor 12; and a second circuit block 2 in which a plurality of nMOS transistors 21 are connected in series or connected to a parallel circuit provided with one nMOS transistor 22, wherein a node S between the first circuit block 1 and the second circuit block 2 is connected to an output terminal Vout, and gates of all the pMOS transistors 11, 12 and gates of all the nMOS transistors 21, 22 are connected to a common input terminal Vin. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过实现具有优异的耐辐射特性的半导体电路来提高装载有半导体电路的电子设备的可靠性。解决方案：半导体电路包括：第一电路块1，其中多个pMOS晶体管11串联连接或连接到具有一个pMOS晶体管12的并联电路; 以及第二电路块2，其中多个nMOS晶体管21串联或连接到具有一个nMOS晶体管22的并联电路，其中第一电路块1和第二电路块2之间的节点S连接到输出端子Vout和所有nMOS晶体管21,22的栅极和所有nMOS晶体管21,22的栅极连接到公共输入端子Vin。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2005302122A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2005302122A
公开(公告)日：2005-10-27
申请号：JP2004115428
申请日：2004-04-09
申请人： Mitsubishi Heavy Ind Ltd , Seiko Epson Corp , セイコーエプソン株式会社 , 三菱重工業株式会社
发明人： TAGUCHI KAZUO , ISHII SHIGERU , KURODA YOSHIKATSU , TAKAHASHI DAISUKE
IPC分类号： G11C11/41 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of guaranteeing a fast operation while improving soft error resistance. SOLUTION: This semiconductor memory device includes a memory cell formed on a silicon-on-insulator (SOI) substrate. The memory cell includes a pair of n type resistande added transistors TN5 and TN6 in which a gate is connected to a word line, and a source and a drain interconnect the input nodes N1 and N2 and the output nodes N3 and N4 of a pair of CMOS inverters INV1 and INV2, and a p type potential compensation transistors TP3 and TP4 in which a source is connected to a high potential power supply line VDD, a drain is connected to the input nodes N1 and N2 of the CMOS inverters INV1 and INV2, and a gate is connected to the input nodes N2 and N1 of the CMOS inverters INV1 and INV2. In the n type resistance added transistors TN5 and TN6, a conductive state is set between the source and the drain when a gate voltage is equal to a low potential power supply line VSS. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够在提高软错误电阻的同时保证快速操作的半导体存储器件。解决方案：该半导体存储器件包括形成在绝缘体上硅（SOI）衬底上的存储单元。存储单元包括一对n型阻抗增加晶体管TN5和TN6，其中栅极连接到字线，源极和漏极互连输入节点N1和N2以及输出节点N3和N4的一对 CMOS反相器INV1和INV2以及其中源极连接到高电位电源线VDD的ap型电位补偿晶体管TP3和TP4，漏极连接到CMOS反相器INV1和INV2的输入节点N1和N2，以及栅极连接到CMOS反相器INV1和INV2的输入节点N2和N1。在n型电阻加法晶体管TN5和TN6中，当栅极电压等于低电位电源线VSS时，在源极和漏极之间设置导通状态。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2004079627A Transistor, electronic circuit, method for operating transistor, and method for using electronic apparatus 审中-公开
标题翻译：晶体管，电子电路，操作晶体管的方法和使用电子装置的方法
公开(公告)号：JP2004079627A
公开(公告)日：2004-03-11
申请号：JP2002234957
申请日：2002-08-12
申请人： Mitsubishi Heavy Ind Ltd , 三菱重工業株式会社
发明人： TAKAHASHI DAISUKE
IPC分类号： H01L29/786
摘要： PROBLEM TO BE SOLVED: To further improve the radiation resistance of a transistor.
SOLUTION: The transistor includes an insulator (2), a semiconductor layer (3) formed on the insulator (2), a gate electrode (8), and a gate insulating layer (7) interposed between the electrode (8) and the layer (3). The layer (3) includes a first conductivity source region (4), a first conductivity drain region (6), and a second conductivity body region (5) different from the first conductivity and interposed between the source region (4) and the drain region (6). The gate electrode (8) is formed so that the body region (5) is covered with the electrode (8). The region (5) has a high impurity concentration, and more particularly, the impurity concentration of the region (5) is 10
20 -10
22 cm
-3 .
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：进一步提高晶体管的耐辐射性。解决方案：晶体管包括绝缘体（2），形成在绝缘体（2）上的半导体层（3），栅极电极（8）和置于电极（8）之间的栅极绝缘层（7）和层（3）。层（3）包括第一导电源区域（4），第一导电漏极区域（6）和与第一导电率不同的第二导电体区域（5），并且介于源极区域（4）和漏极区域（6）。栅电极（8）形成为使得主体区域（5）被电极（8）覆盖。区域（5）具有高的杂质浓度，更具体地说，区域（5）的杂质浓度为10 20 22 。版权所有（C）2004，JPO

5. 发明专利

JP2006066484A Semiconductor circuit 有权
标题翻译：半导体电路
公开(公告)号：JP2006066484A
公开(公告)日：2006-03-09
申请号：JP2004244714
申请日：2004-08-25
申请人： Mitsubishi Heavy Ind Ltd , 三菱重工業株式会社
发明人： ISHII SHIGERU , YAMAMOTO KENSUKE , TAKAHASHI DAISUKE
IPC分类号： H01L21/8238 , H01L21/822 , H01L27/04 , H01L27/08 , H01L27/092 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor circuit having an excellent radiation resistant property.
SOLUTION: The semiconductor circuit comprises a first circuit block 1 where one pMOS transistor 11 is connected in series with at least the other one pMOS transistor 12 or a parallel circuit provided with at least the other one pMOS transistor and common signals are inputted to gates of the pMOS transistor 11 and the other one pMOS transistor 12, and/or a second circuit block 2 where one nMOS transistor 21 is connected in series with at least the other one nMOS transistor 22 or a parallel circuit provided with at least the other one nMOS transistor and common signals are inputted to gates of the nMOS transistor 21 and the other one nMOS transistor 22.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供具有优异耐辐射性的半导体电路。解决方案：半导体电路包括第一电路块1，其中一个pMOS晶体管11至少与另一个pMOS晶体管12串联或至少设置有至少另一个pMOS晶体管并且输入公共信号的并联电路到pMOS晶体管11和另一个pMOS晶体管12的栅极和/或第二电路块2，其中一个nMOS晶体管21与至少另一个nMOS晶体管22串联连接，或者至少设置有至少另一个nMOS晶体管和公共信号被输入到nMOS晶体管21和另一个nMOS晶体管22的栅极。（C）2006，JPO和NCIPI

6. 发明专利

JP2005302124A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2005302124A
公开(公告)日：2005-10-27
申请号：JP2004115430
申请日：2004-04-09
申请人： Mitsubishi Heavy Ind Ltd , Seiko Epson Corp , セイコーエプソン株式会社 , 三菱重工業株式会社
发明人： TAGUCHI KAZUO , ISHII SHIGERU , KURODA YOSHIKATSU , TAKAHASHI DAISUKE
IPC分类号： G11C11/41 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of guaranteeing a fast operation while soft error resistance is increased.
SOLUTION: This semiconductor memory device includes a memory cell formed on a silicon-on-insulator (SOI) substrate. The memory cell includes a pair of n type resistance added transistors TN5 and TN6 in which a gate is connected to a word line WL, a body is connected to the output nodes N3 and N4 of a pair of inverters INV1 and INV2, and a source and a drain interconnect the input nodes N1 and N2 and the output nodes N3 and N4 of the pair of inverters INV1 and INV2. The n type resistance added transistors TN5 and TN6 are source tie (ST) type MOS transistors, and a conductive state is set between the source and the drain in the nonaccessed state of the memory cell.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体存储器件，其能够在提高柔软的抗错误性的同时保证快速操作。解决方案：该半导体存储器件包括形成在绝缘体上硅（SOI）衬底上的存储单元。存储单元包括一对n型电阻加法晶体管TN5和TN6，其中栅极连接到字线WL，主体连接到一对反相器INV1和INV2的输出节点N3和N4，源极并且漏极互连输入节点N1和N2以及该对反相器INV1和INV2的输出节点N3和N4。 n型电阻添加晶体管TN5和TN6是源极（ST）型MOS晶体管，并且在存储单元的非处理状态下的源极和漏极之间设置导通状态。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2013085272A Semiconductor circuit 审中-公开
标题翻译：半导体电路
公开(公告)号：JP2013085272A
公开(公告)日：2013-05-09
申请号：JP2012269770
申请日：2012-12-10
申请人： Mitsubishi Heavy Ind Ltd , 三菱重工業株式会社
发明人： ISHII SHIGERU , YAMAMOTO KENSUKE , TAKAHASHI DAISUKE
IPC分类号： H03K19/003 , H01L21/822 , H01L27/04 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor circuit having excellent radiation-resistant characteristics.SOLUTION: A semiconductor circuit includes a first circuit block 1 in which a plurality of pMOS transistors 11 and 12 are connected in series, and a second circuit block 2 in which a plurality of nMOS transistors 21 and 22 are connected in series. A gate of at least one pMOS transistor 12 and/or a gate of at least one nMOS transistor 21 are/is connected to an input terminal Vin, and an on-voltage is applied to a gate of at least one the other pMOS transistor 11 and/or a gate of at least one the other nMOS transistor 22.
摘要翻译：要解决的问题：提供具有优异耐辐射特性的半导体电路。解决方案：半导体电路包括其中多个pMOS晶体管11和12串联连接的第一电路块1和多个nMOS晶体管21和22串联连接的第二电路块2。至少一个pMOS晶体管12的栅极和/或至少一个nMOS晶体管21的栅极被连接到输入端Vin，并且将导通电压施加到至少一个其它pMOS晶体管11的栅极和/或至少另一个nMOS晶体管22的栅极。（C）2013，JPO和INPIT

8. 发明专利

JP2005302123A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2005302123A
公开(公告)日：2005-10-27
申请号：JP2004115429
申请日：2004-04-09
申请人： Mitsubishi Heavy Ind Ltd , Seiko Epson Corp , セイコーエプソン株式会社 , 三菱重工業株式会社
发明人： TAGUCHI KAZUO , ISHII SHIGERU , KURODA YOSHIKATSU , TAKAHASHI DAISUKE
IPC分类号： G11C11/41 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of guaranteeing a fast operation while soft error resistance is increased.
SOLUTION: This semiconductor memory device includes a memory cell formed in a silicon-on-insulator (SOI) substrate. The memory cell includes a plurality of n type resistance added transistors TN5 to TN8 in which a source and a drain are serially connected between the input nodes N1 and N2 and the output nodes N3 and N4 of a pair of inverters INV1 and INV2, and a pair of resistance added transistor groups TNG1 and TNG2 for interconnecting the pair of inverters INV1 and INV2. The n type resistance added transistors TN5 to TN8 are depression type transistors having threshold values equal to/less than 0, a gate is connected to a word line WL, and a conductive state is set between the source and the drain when a gate voltage is equal to a low potential power supply line VSS.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体存储器件，其能够在提高柔软的抗错误性的同时保证快速操作。解决方案：该半导体存储器件包括形成在绝缘体上硅（SOI）衬底中的存储单元。存储单元包括多个n型电阻加法晶体管TN5至TN8，其中源极和漏极串联连接在输入节点N1和N2与一对反相器INV1和INV2的输出节点N3和N4之间，并且一对电阻加法晶体管组TNG1和TNG2，用于互连该对反相器INV1和INV2。 n型电阻加法晶体管TN5至TN8是具有等于/小于0的阈值的凹陷型晶体管，栅极连接到字线WL，并且当栅极电压为栅极电压时，导通状态被设置在源极和漏极之间等于低电位电源线VSS。版权所有（C）2006，JPO＆NCIPI

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