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1. 发明专利

JP2011153268A Resin composition and a cured resin 审中-公开
标题翻译：树脂组合物和树脂固化产品
公开(公告)号：JP2011153268A
公开(公告)日：2011-08-11
申请号：JP2010017248
申请日：2010-01-28
申请人： Mitsubishi Electric Corp , Tokyo Institute Of Technology , 三菱電機株式会社 , 国立大学法人東京工業大学
发明人： YASUDA NAOKI , KAKIMOTO MASAAKI , URUSHIBATA HIROAKI , HAYAKAWA TERUAKI , MAEDA RINA , KODAMA TAKASHI
IPC分类号： C08L101/02 , C08F2/44 , C08F16/28 , C08G59/20 , H01B3/30 , H01B3/40
摘要： PROBLEM TO BE SOLVED: To provide a resin composition giving a uniform resin cured product of high electric insulating performance and thermal conductivity, and excellent in moldability, and to provide the uniform resin cured product of high electric insulating performance and thermal conductivity. SOLUTION: This resin composition of the invention contains a compound having a main chain including a benzazole skeleton, and branch chains bonded to both ends of the main chain and including a polymerizable group in a terminal. The resin cured product of the invention is obtained by polymerizing the resin composition. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供具有高电绝缘性能和导热性，成型性优异的均匀树脂固化产物的树脂组合物，并提供具有高电绝缘性能和导热性的均匀树脂固化产物。解决方案：本发明的该树脂组合物含有具有包含苯并恶唑骨架的主链的化合物和在主链的两端键合并在末端具有聚合性基团的分支链。本发明的树脂固化物通过树脂组合物的聚合得到。版权所有（C）2011，JPO＆INPIT

2. 发明专利

DE4122385A1 未知
公开(公告)号：DE4122385A1
公开(公告)日：1992-01-30
申请号：DE4122385
申请日：1991-07-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： KODAMA TAKASHI
IPC分类号： G06F9/38 , G06F15/16 , G06F15/177 , G06F15/80
摘要： A parallel processing system wherein the instruction field of each instruction is additionally provided with execution predict count information representative of the number of basic clocks required to execute the instruction, and sort circuits that rearrange a group of instructions on the basis of the execution predict count information are provided and wherein the group of instructions are divided into a plurality of blocks in units of columns, as a prefetching processing, and the blocks of instructions prefetched in units of columns are alternately subjected to sorting in descending order and sorting in ascending order by the sort circuits on the basis of the execution predict count information.

3. 发明专利

DE4122385C2 未知
公开(公告)号：DE4122385C2
公开(公告)日：1994-01-20
申请号：DE4122385
申请日：1991-07-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： KODAMA TAKASHI
IPC分类号： G06F9/38 , G06F15/177 , G06F15/80 , G06F15/16 , G06F7/00
摘要： A parallel processing system wherein the instruction field of each instruction is additionally provided with execution predict count information representative of the number of basic clocks required to execute the instruction, and sort circuits that rearrange a group of instructions on the basis of the execution predict count information are provided and wherein the group of instructions are divided into a plurality of blocks in units of columns, as a prefetching processing, and the blocks of instructions prefetched in units of columns are alternately subjected to sorting in descending order and sorting in ascending order by the sort circuits on the basis of the execution predict count information.

4. 发明专利

JPS6437640A CONTROL SYSTEM FOR CACHE MEMORY 失效
公开(公告)号：JPS6437640A
公开(公告)日：1989-02-08
申请号：JP19389987
申请日：1987-08-03
申请人： MITSUBISHI ELECTRIC CORP
发明人： KODAMA TAKASHI
IPC分类号： G06F12/08
摘要： PURPOSE:To set up block size for maximizing the performance of a system by providing the titled system with a switching means for switching the block size of a cache memory. CONSTITUTION:Data to be complicatedly accessed from a processing part 1A to a main storage device 1B are temporarily stored in the cache memory 1C of a cache part 11D and the data are successively updated in each block so that the data to be complicatedly accessed by the processing part 1A are always stored. In case of accessing data, the processing part 1a checks whether data exist in the memory 1C or not, and when the data exist, the memory 1C is accessed. At the time of absence of data, the main storage device 1B is accessed. The control part 1D in the cache part 11D is provided with the switching means 10D for switching the block size of the memory 1C and the block size for maximizing the performance of the system is set up in the switching means 10D.

5. 发明专利

JPS61208560A SEPARATING STRUCTURE BETWEEN EQUIPMENTS OF DEVICE 失效
公开(公告)号：JPS61208560A
公开(公告)日：1986-09-16
申请号：JP4991385
申请日：1985-03-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： KODAMA TAKASHI
IPC分类号： G06F13/40
摘要： PURPOSE:To make easy an expansion and a reduction of a system by having an end resistance module outside a system by feeding a power source line from a controller and distributing a signal cable on a junction panel. CONSTITUTION:Junction panels 12, 14 have an input and output ports of a signal line. Respective devices 2, 5 are connected to the respective junction palens 12, 14 by signal cables 9, 10. The junction panel 12 is connected to a controller by a signal cable 11 and the junction panel 14 is connected to the junction panel 12 by a signal cable 17. An end resistance module 8 is connected to the junction panel 14.

6. 发明专利

JPH0421048A CACHE MEMORY DEVICE 失效
公开(公告)号：JPH0421048A
公开(公告)日：1992-01-24
申请号：JP12363890
申请日：1990-05-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： KODAMA TAKASHI
IPC分类号： G06F12/12
摘要： PURPOSE:To effectively utilize the memory bus, and also, to omit the drawback register group by executing alternately a data transfer from other memory based on a request address and a transfer of replace data to other memory, when a dirty flag of the replace data is turned on. CONSTITUTION:A comparing part 107 detects a mishit by comparing a request address with a directory 104, a cache controller 108 inspects an address part of a replace block due to a fact that the comparing part detects the mishit, and also, when a dirty flag of this address part is turned on, a data transfer from other memory based on a request address and a transfer of replace data to other memory are executed alternately. Subsequently, an address generating part 109 outputs each address of a data transfer request from other memory and a transfer request of the replace data to other memory. In such a way, memory buses 21, 22 are utilized effectively, and also, a drawback register group is omitted.

7. 发明专利

JPH038023A BRANCH PREDICTING ALGORITHM 失效
公开(公告)号：JPH038023A
公开(公告)日：1991-01-16
申请号：JP14328189
申请日：1989-06-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： KODAMA TAKASHI
IPC分类号： G06F9/38
摘要： PURPOSE:To increase a branch predicting condition and to improve the rate of success for predicting a branch by providing more than three kinds of branch status for a branch predicting algorithm and increasing the history of the branch. CONSTITUTION:The branch is expressed by T and a negative branch is expressed by N. For example, in the case of NTNT, the branch and negative branch are repeated. In such a case, since it can be predicted that the branch and negative branch are repeated in following operation, such a state is predicted as N. The case of TNTN is samely predicted as T. Next, in the case of NNNT, concerning a branch instruction after arithmetic calculation, since the instruction is defined to execute the branch only when a digit flows over, such a state is predicted as N. In the case of TTTN, when a counter is not 0, such a state can be predicted as T and in the case of NNTN, such a state can be predicted as N similary as the case of NNNT. When it is failed to predict NTTN and TNNT, NTTN is transited to TTNN. Accordingly, the next state can be predicted as N and accuracy for predicting is improved in the following operation. Samely, since TNNT is transited to NNTT, the next state is predicted as T and the accuracy for predicting the following branch is improved.

8. 发明专利

JPS6120424A Logical circuit 失效
标题翻译：逻辑电路
公开(公告)号：JPS6120424A
公开(公告)日：1986-01-29
申请号：JP14026684
申请日：1984-07-06
申请人： Mitsubishi Electric Corp
发明人： KODAMA TAKASHI
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/01
CPC分类号： H03K19/00
摘要： PURPOSE:To process a signal at a high speed by generating in advance by a logical operation the first output signal in case when it is assumed that logic of a binary signal is ''0'', and the second output signal in case when it is assumed that logic of the binary signal is ''1'', with respect to the binary signal which is delayed and inputted. CONSTITUTION:In logical circuits 1a, 1b, in the circuit 1a, a signal of logic ''0'' and logic ''L'' is connected to a terminal 4a corresponding to a terminal 4 to which a signal C is inputted by a circuit 1, and in the circuit 1b, a signal of logic ''1'' and logic ''H'' is connected to a terminal 4b. Accordingly, after a processing time tau from a time point t0 when signals A and B have arrived, output signals of terminals 5a, 5b are settled and inputted to a selector 6. Therefore, at the time point t1 when the signal C has arrived, one of the signals from the terminal 5a or 5b is outputted as an output signal D, therefore, the time between the input time point t0 of the signals A, B and the output time point t1 of the signal D goes to t1-t0, and it is shortened comparing with the conventional (t1-t0)+tau.
摘要翻译：目的：通过在假设二进制信号的逻辑为“0”的情况下通过逻辑运算产生第一输出信号来高速处理信号，而在第二输出信号假设二进制信号的逻辑对于被延迟和输入的二进制信号是“1”。构成：在逻辑电路1a，1b中，在电路1a中，将逻辑“0”和逻辑“L”的信号连接到对应于输入信号C的端子4的端子4a 电路1中，并且在电路1b中，将逻辑“1”和逻辑“H”的信号连接到端子4b。因此，在信号A，B到达时间点t0的处理时间τ以后，端子5a，5b的输出信号被置位并输入到选择器6.因此，在信号C到达时刻t1，输出端子5a或5b的信号之一作为输出信号D，因此信号A，B的输入时刻t0与信号D的输出时刻t1之间的时间变为t1-t0，并且与常规（t1-t0）+ tau相比缩短。

9. 发明专利

JPS6055455A HIGH-SPEED BUFFER STORAGE DEVICE 失效
公开(公告)号：JPS6055455A
公开(公告)日：1985-03-30
申请号：JP16361283
申请日：1983-09-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： KODAMA TAKASHI
IPC分类号： G06F12/08 , G06F12/10
摘要： PURPOSE:To detect accurately a decrease in hit rate and to generate a warning by adding a hit rate detecting circuit to a cache memory. CONSTITUTION:A request regenerating circuit 5 outputs a request signal every time a request signal 7 arrives. A signal output of main storage fetch sets FF9, and a signal output of main storage store sets FF10; and a signal output of cache memory fetch sets FF11, and a signal output of cache memory store sets FF12. Then AND circuits 23 and 24 are turned on by the output of a clock generating circuit 13 to count the output of an OR circuit 21 by a counter 14 and the output of an OR circuit 22 by a counter 15, and the FFs 9-12 are reset after the counting is completed. The ratio of the counted value of the counter 15 to that of the counter 14 corresponds to the hit rate. Then, a warning signal is outputted through an arithmetic circuit 17, hit rate register 18, and hit rate checking circuit 19.

10. 发明专利

JPH0475159A PARALLEL PROCESSING SYSTEM 失效
公开(公告)号：JPH0475159A
公开(公告)日：1992-03-10
申请号：JP18899790
申请日：1990-07-17
申请人： MITSUBISHI ELECTRIC CORP
发明人： KODAMA TAKASHI
IPC分类号： G06F15/16 , G06F9/38 , G06F15/177 , G06F15/80
摘要： PURPOSE:To efficiently perform parallel processing by dividing an instruction group into several blocks in unit of column, and performing the sorting of the block representing the maximum value and that of the block representing the minimum value out of execution predictive count information on a pre-fetch string alternately. CONSTITUTION:The processing elements 2a-2e of an arithmetic processing part provided at a parallel computer and instruction queues 4a-4c which supply instructions to the elements are provided. Sort circuits 5a-5e, 6a-6e which attach the execution predictive count information of the instruction on an instruction field part 30 and furthermore, re-arrange the instruction group based on the execution predictive count information are provided. At this time, the instruction group is divided into the several blocks in unit of column as pre-fetch processing, and the sorting of the block representing the maximum value and that of the block representing the minimum value out of the execution predictive count information are performed on the pre-fetch string alternately by the sort circuits 5a-5e, 6a-6e. Thereby, the instruction group can be re-arranged so as to average instruction execution time, and the overhead of processing can be reduced, and the parallel processing with high efficiency can be executed.

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