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1. 发明专利

JP2011150486A Data processing apparatus 审中-公开
标题翻译：数据处理设备
公开(公告)号：JP2011150486A
公开(公告)日：2011-08-04
申请号：JP2010010400
申请日：2010-01-20
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NISHIKAWA KOJI
IPC分类号： G06F12/16
摘要： PROBLEM TO BE SOLVED: To speed up memory access in partial access if data and ECC data are arranged in a same memory. SOLUTION: An area management part 11 divides a memory 2 into a cache area and a uncacheable area, sets a control object data size targeted by the ECC data as one byte or the like correspondingly to the partial access for the uncacheable area, and sets ECC data for data of the control object data size. If an access request from a CPU 1 is for a uncacheable area, data are read or written according to the control object data size in the uncacheable area, error-correction during reading and generation of ECC data during writing are performed for data of the control object data size in the uncacheable area, thus eliminating the need for waiting for processing for data except read data or write data, and the memory access in the partial access is accelerated. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：如果数据和ECC数据被布置在同一个存储器中，则加速部分访问中的存储器访问。解决方案：区域管理部分11将存储器2划分为高速缓存区域和不可缓存区域，将与ECC数据对应的控制对象数据大小设置为与不可缓存区域的部分访问相对应的一个字节等，并设置用于控制对象数据大小的数据的ECC数据。如果来自CPU 1的访问请求用于不可缓存的区域，则根据不可缓存区域中的控制对象数据大小读取或写入数据，在读取期间进行纠错并且在写入期间对控制数据执行ECC数据的生成对象数据大小，因此不需要等待处理除了数据或写数据之外的数据，并且部分访问中的存储器访问被加速。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2005157640A Instruction simulation device, instruction simulation method and instruction simulation program 有权
标题翻译：指令仿真器件，指令仿真方法和指令仿真程序
公开(公告)号：JP2005157640A
公开(公告)日：2005-06-16
申请号：JP2003393977
申请日：2003-11-25
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NISHIKAWA KOJI , TAKEO TETSUYA
IPC分类号： G06F9/455
摘要： PROBLEM TO BE SOLVED: To streamline a simulation according to whether or not there is a simulation instruction corresponding to a target program.
SOLUTION: An instruction simulation device for simulating an instruction of an object of simulation (target) by an instruction of a simulation computer comprises a conversion information analysis part 300 for analyzing the instruction of the object of simulation irrespective of an execution history to extract/assign necessary information, a pointer reference information holding part 400 for storing information including state information indicating whether or not there is a simulation instruction described in an instruction set of the simulation computer for the analyzed/extracted instruction, and an execution part 600 for, when simulating the instruction of the object of simulation, referring to the state information stored in the pointer reference information holding part, and if it corresponds to an already simulated instruction, executing the corresponding simulation instruction; otherwise sequentially fetching, analyzing and executing the instruction of the object of simulation.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：根据是否存在与目标程序相对应的模拟指令来简化模拟。解决方案：用于通过仿真计算机的指令模拟仿真对象（目标）的指令的指令模拟装置包括转换信息分析部分300，用于分析仿真对象的指令，而不管执行历史如何提取/分配必要信息，用于存储信息的指针参考信息保持部分400，包括指示是否存在用于分析/提取的指令的模拟计算机的指令集中描述的模拟指令的状态信息的信息;以及执行部分600，参照存储在指针参考信息保持部分中的状态信息，并且如果它对应于已经模拟的指令，则执行相应的仿真指令，当模拟仿真对象的指令时，否则顺序地获取，分析和执行仿真对象的指令。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2004265344A Processor simulator 审中-公开
公开(公告)号：JP2004265344A
公开(公告)日：2004-09-24
申请号：JP2003057531
申请日：2003-03-04
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TAKEO TETSUYA , NISHIKAWA KOJI , OMIYA YASUTO
IPC分类号： G06F9/455
摘要： PROBLEM TO BE SOLVED: To reduce memory capacity and increase simulation speed by analyzing object codes and converting and sequentially mapping only codes to be simulated.
SOLUTION: A processor simulator comprises an unnecessary code detection part 50 for detecting unexecuted instructions in instruction codes to be checked, and an instruction code remapping part 70 for deleting the detected unnecessary codes and moving the addresses of and remapping the instruction code sequence after the deletion according to given rules.
COPYRIGHT: (C)2004,JPO&NCIPI

4. 发明专利

JP2014182509A Logic verification device, logic verification method and logic verification program 审中-公开
标题翻译：逻辑验证设备，逻辑验证方法和逻辑验证程序
公开(公告)号：JP2014182509A
公开(公告)日：2014-09-29
申请号：JP2013055603
申请日：2013-03-18
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TAKEO TETSUYA , NISHIKAWA KOJI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To make logic verification more efficient and shorten a verification period by correcting a test pattern while continuing a verification simulation of a logic circuit.SOLUTION: A logic verification device comprises: an event table 121 that defines an event occurrence condition consisting of at least one single condition; a condition occurrence table 120 that describes satisfaction method information for increasing occurrence frequency of the single condition; coverage information 110 that stores the number of event occurrences; and a pattern-generation-control change instruction unit 108 that extracts a single condition constituting the occurrence information for the event with a small number of occurrences from the event table 121, extracts the satisfaction method information for the extracted single condition from the occurrence table 120, generates control change instruction information for correcting a test pattern 103 and outputs the generated information to a pattern generation control unit 102.
摘要翻译：要解决的问题：通过在继续逻辑电路的验证模拟的同时修正测试模式，使逻辑验证更有效并缩短验证周期。解决方案：逻辑验证设备包括：事件表121，其定义事件发生条件，包括至少一个单一条件; 描述用于增加单个条件的发生频率的满足方法信息的条件发生表120; 存储事件发生次数的覆盖信息110; 以及从事件表121提取构成具有少数事件的事件的发生信息的单个条件的模式生成控制改变指示单元108从出现表120中提取提取的单个条件的满足方法信息生成用于校正测试图案103的控制改变指令信息，并将生成的信息输出到图案生成控制单元102。

5. 发明专利

JP2013222392A Information processing device, information processing method, and program 审中-公开
标题翻译：信息处理设备，信息处理方法和程序
公开(公告)号：JP2013222392A
公开(公告)日：2013-10-28
申请号：JP2012094809
申请日：2012-04-18
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NISHIKAWA KOJI
IPC分类号： G06F9/455 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To improve calculation accuracy of a program execution time by an instruction set simulation.SOLUTION: An instruction interpreter unit 50 simulates execution processing of a branch instruction of a processor predicting a branch. A branch instruction delay model unit 320 simulates the branch prediction of the processor. The branch instruction delay model unit 320 compares an execution processing result with the branch prediction for every branch instruction, and predicts a delay time when the processor executes a branch instruction where the branch has been correctly predicted or a branch instruction where the branch has not been correctly predicted. This configuration can improve calculation accuracy of a program execution time by the instruction set simulation.
摘要翻译：要解决的问题：通过指令集模拟来提高程序执行时间的计算精度。解决方案：指令解释器单元50模拟预测分支的处理器的分支指令的执行处理。分支指令延迟模型单元320模拟处理器的分支预测。分支指令延迟模型单元320将执行处理结果与每个分支指令的分支预测进行比较，并且当处理器执行分支已被正确预测的分支指令或分支未被分支的分支指令时，预测延迟时间正确预测该配置可以通过指令集仿真提高程序执行时间的计算精度。

6. 发明专利

JP2010211342A Test pattern management device, test pattern management method, and program 审中-公开
标题翻译：测试模式管理设备，测试模式管理方法和程序
公开(公告)号：JP2010211342A
公开(公告)日：2010-09-24
申请号：JP2009054420
申请日：2009-03-09
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TAKEO TETSUYA , NISHIKAWA KOJI
IPC分类号： G06F17/50 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To efficiently generate a test pattern which enables an effective simulation.
SOLUTION: An initial probability setting file 13 shows the rate of each parameter value for each parameter item, and a test parameter generator 2 generates a plurality of types of test patterns according to a rate of each parameter value of the initial probability setting file 13, and makes a test bench 4 execute simulation by using a test pattern 3. A result file input part 14 inputs a result file 6 showing the result of simulation, and stores it in an execution log 7, and a failure history analyzing part 9 analyzes a failure factor history 8 showing the factor of a failure test pattern obtained from the execution log 7, and a probability setting file generator 10 generates a new probability setting file 1 by increasing the rate of the parameter value whose failure generation frequency is high, and the test pattern generator 2 generates a new test pattern 3 according to the probability setting file 1.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：有效地生成能够进行有效模拟的测试图案。解决方案：初始概率设置文件13显示每个参数项的每个参数值的速率，测试参数生成器2根据初始概率设置的每个参数值的速率生成多种类型的测试模式文件13，并且使测试台4通过使用测试模式3执行模拟。结果文件输入部分14输入示出仿真结果的结果文件6，并将其存储在执行日志7中，以及故障历史分析部分图9分析表示从执行日志7获得的故障测试模式的因子的故障因子历史8，概率设置文件生成器10通过增加故障发生频率高的参数值的比率来生成新概率设置文件1 ，并且测试图案生成器2根据概率设置文件1生成新的测试模式3.版权所有：（C）2010，JPO＆INPIT

7. 发明专利

JP2008305027A Information processor, communication system, information processing method and program 审中-公开
标题翻译：信息处理器，通信系统，信息处理方法和程序
公开(公告)号：JP2008305027A
公开(公告)日：2008-12-18
申请号：JP2007149656
申请日：2007-06-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTAKI HIROSHI , KAMEMARU TOSHIHISA , NISHIKAWA KOJI
IPC分类号： G08G1/16 , B60R21/00
摘要： PROBLEM TO BE SOLVED: To notify the presence of a two-wheel vehicle to a four-wheel vehicle by determining a moving direction of the two-wheel vehicle by one reader device. SOLUTION: RFID tags 6 and 7 are stuck to both side surface of the two-wheel vehicle. An RFID reader device 11 of an RFID tag detection/RFID tag data transmitting device 1 set on a roadside reads the tags, detects an running direction of the two-wheel vehicle by comparing receiving sensitivities of the tags, and transmits information for two-wheel vehicle to an antenna 4 disposed at an intersection, when the two-wheel vehicle approaches the intersection, to transmit the information to a four-wheel vehicle near the intersection. An RFID tag data receiving/receiving data display alarm device 2 mounted on the four-wheel vehicle receives the information for two-wheel vehicle, a receiving data selection part 23 determines the probability of a collision accident between the four-wheel vehicle and the two-wheel vehicle, and a receiving data display/alarm part 24 warns of the presence of the two-wheel vehicle to a driver when the four-wheel vehicle is in danger of an accident. According to this, the two-wheel vehicle unrecognized by the driver can be recognized to prevent an accident. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过一个读取器装置确定两轮车辆的移动方向，来向四轮车辆通知两轮车辆的存在。解决方案：RFID标签6和7粘在两轮车的两侧面上。设置在路边的RFID标签检测/ RFID标签数据发送装置1的RFID读取装置11读取标签，通过比较标签的接收灵敏度来检测二轮车的行驶方向，并发送用于两轮的信息车辆到设置在交叉路口的天线4，当两轮车辆接近交叉路口时，将信息发送到交叉口附近的四轮车辆。安装在四轮车上的RFID标签数据接收/接收数据显示报警装置2接收二轮车的信息，接收数据选择部23确定四轮车与二轮车之间碰撞事故的可能性并且当四轮车辆处于事故危险时，接收数据显示/报警部分24向驾驶员警告两轮车辆的存在。据此，能够识别驾驶员无法识别的两轮车辆，以防止事故。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2006163565A Sort processor, sort processing method and program 有权
标题翻译：排序处理器，排序处理方法和程序
公开(公告)号：JP2006163565A
公开(公告)日：2006-06-22
申请号：JP2004350983
申请日：2004-12-03
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TAKEO TETSUYA , NISHIKAWA KOJI
IPC分类号： G06F7/24 , G06F12/08
摘要： PROBLEM TO BE SOLVED: To improve a cache hit ratio while speeding up sort processing to a large capacity of sorting object data on a main memory. SOLUTION: A block division part 10 acquires information for a primary cache and a secondary cache of a CPU to be used for sort processing from a CPU information holding part 102, calculates a block size for dividing sort object data 2 on the basis of the cache sizes of the primary cache and the secondary cache, and divides the sort object data to a plurality of blocks on the basis of the calculated block size. A block internal sort processing part 4 performs block internal sort for each block divided by the block division part 10 by use of the secondary cache of the CPU, and a block-to-block merge processing part 5 merges each block sorted by the block internal sort processing part 4 by use of the primary cache to sort the sorting object data, and outputs sorting result data 3 after sorting to a main storage 1. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提高缓存命中率，同时加快排序处理，以便在主存储器上排序对象数据的大容量。解决方案：块分割部分10从CPU信息保持部分102获取要用于分类处理的CPU的主高速缓存和二级高速缓存的信息，基于该方法计算用于划分分类对象数据2的块大小的一级缓存和二级高速缓存的高速缓存大小，并且基于所计算的块大小将排序对象数据划分为多个块。块内部分类处理部分4通过使用CPU的二次高速缓存来对由块分割部分10分割的每个块执行块内部排序，并且块到块合并处理部分5将由块内部排序的每个块合并通过使用主缓存对排序对象数据进行排序处理部分4，并且将排序结果数据3输出到主存储器1之后输出。（C）2006年，JPO＆NCIPI

9. 发明专利

JP2004157642A Processor simulator 审中-公开
公开(公告)号：JP2004157642A
公开(公告)日：2004-06-03
申请号：JP2002320860
申请日：2002-11-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NISHIKAWA KOJI
IPC分类号： G06F9/455
摘要： PROBLEM TO BE SOLVED: To reduce an imitating scale, and to shorten a processing time in a system of a host processor imitating a target processor.
SOLUTION: When checkpoint execution which means a hardware resource update is performed in processing after code conversion, a checkpoint detecting part for detecting the checkpoint execution is provided, and the processing is performed by converted the code (S6) while the execution of the checkpoint is performed. When the host processor detects unexpected exception processing, processing (S8) for restoring the checkpoint immediately before the detected point is performed.
COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2014153755A Multiprocessor built-in apparatus 有权
标题翻译：多功能内置设备
公开(公告)号：JP2014153755A
公开(公告)日：2014-08-25
申请号：JP2013020491
申请日：2013-02-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： NISHIKAWA KOJI
IPC分类号： G06F9/50 , G06F9/48 , G06F13/362
摘要： PROBLEM TO BE SOLVED: To provide a multiprocessor built-in apparatus capable of minimizing the increase of processing time due to access concentration of a program assignment from a processor to a processor to a bus slave in consideration of behavior in other processors.SOLUTION: In order to be used as a reference when a program is assigned to each processor, the number of access requests from a bus master to a bus slave and each latency from an access request issued from the bus master to a responce to the access request at the bus slave, until bus slave processing is started by the access request from the bus master and from the access request issued from the bus master to a response to the access request at the bus slave are measured for each combination of bus masters 10, 20 and 30 with bus slaves 100, 200 and 300.
摘要翻译：要解决的问题：考虑到其他处理器中的行为，提供一种多处理器内置设备，其能够最小化由于从处理器到处理器到总线从站的程序分配的访问集中而导致的处理时间的增加。解决方案：当将程序分配给每个处理器时，作为参考的顺序，从总线主机到总线从站的访问请求的数量以及从总线主机发出的访问请求的响应时间以及响应于访问请求总线从站，直到总线主控器的访问请求和从总线主控器发出的访问请求到总线从站的访问请求的响应开始总线从站处理为总线主站10,20的每个组合和 30与公共汽车从站100,200和300。

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