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1. 发明申请

US20050155004A1 Simulation model for design of semiconductor device, thermal drain noise analysis method, simulation method, and simulation apparatus 失效
标题翻译：半导体器件设计仿真模型，散热噪声分析方法，仿真方法和仿真设备
公开(公告)号：US20050155004A1
公开(公告)日：2005-07-14
申请号：US11009094
申请日：2004-12-13
申请人： Mitiko Miura , Hiroaki Ueno , Satoshi Hosokawa
发明人： Mitiko Miura , Hiroaki Ueno , Satoshi Hosokawa
IPC分类号： G01J5/00 , G06F7/60 , G06F17/10 , G06F17/50 , G06G7/62 , H01L21/336 , H01L21/66 , H01L23/58 , H01L29/00 , H01L29/78
CPC分类号： G06F17/5036 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device simulation method includes the step of storing, in a storage unit, a surface potential and threshold voltage obtained by computation, the step of computing thermal drain noise on the basis of the data of the surface potential and thermal drain noise stored in the storage unit, and the step of determining whether or not to reduce thermal drain noise, and reflecting the computation result in simulation of the model when it is determined that thermal drain noise is to be reduced. A drain current Ids of a MOSFET is calculated and substituted into a relational expression for a drain current noise spectrum density obtained from a Nyquist theorem equation, thereby calculating a thermal drain noise coefficient γ of the MOSFET by substituting the current Ids into a relational expression for a thermal drain noise spectrum density which is obtained from the Nyquist logical equation.
摘要翻译：半导体器件模拟方法包括以下步骤：在存储单元中存储通过计算获得的表面电位和阈值电压;基于存储在所述存储器中的表面电位和散热噪声的数据来计算热耗散噪声的步骤存储单元，以及确定是否减少热耗散噪声的步骤，并且当确定要降低热耗散噪声时，反映该模型的模拟中的计算结果。计算MOSFET的漏极电流I SUB，并将其替换为从奈奎斯特定理方程式获得的漏极电流噪声频谱密度的关系式，从而通过替代来计算MOSFET的热耗散噪声系数γ 将当前的I 转换成从奈奎斯特逻辑方程获得的热释放噪声频谱密度的关系表达式。

2. 发明授权

US07213218B2 Simulation model for design of semiconductor device, thermal drain noise analysis method, simulation method, and simulation apparatus 失效
标题翻译：半导体器件设计仿真模型，散热噪声分析方法，仿真方法和仿真设备
公开(公告)号：US07213218B2
公开(公告)日：2007-05-01
申请号：US11009094
申请日：2004-12-13
申请人： Mitiko Miura , Hiroaki Ueno , Satoshi Hosokawa
发明人： Mitiko Miura , Hiroaki Ueno , Satoshi Hosokawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device simulation method includes the step of storing, in a storage unit, a surface potential and threshold voltage obtained by computation, the step of computing thermal drain noise on the basis of the data of the surface potential and thermal drain noise stored in the storage unit, and the step of determining whether or not to reduce thermal drain noise, and reflecting the computation result in simulation of the model when it is determined that thermal drain noise is to be reduced. A drain current Ids of a MOSFET is calculated and substituted into a relational expression for a drain current noise spectrum density obtained from a Nyquist theorem equation, thereby calculating a thermal drain noise coefficient γ of the MOSFET by substituting the current Ids into a relational expression for a thermal drain noise spectrum density which is obtained from the Nyquist logical equation.
摘要翻译：半导体器件模拟方法包括以下步骤：在存储单元中存储通过计算获得的表面电位和阈值电压;基于存储在所述存储器中的表面电位和散热噪声的数据来计算热耗散噪声的步骤存储单元，以及确定是否减少热耗散噪声的步骤，并且当确定要降低热耗散噪声时，反映该模型的模拟中的计算结果。计算MOSFET的漏极电流I SUB，并将其替换为从奈奎斯特定理方程式获得的漏极电流噪声频谱密度的关系式，从而通过替代来计算MOSFET的热耗散噪声系数γ 将当前的I 转换成从奈奎斯特逻辑方程获得的热释放噪声频谱密度的关系表达式。

3. 发明授权

US07735034B2 Simulation model for a semiconductor device describing a quasi-static density of a carrier as a non-quasi-static model 失效
标题翻译：用于描述作为非准静态模型的载波的准静态密度的半导体器件的仿真模型
公开(公告)号：US07735034B2
公开(公告)日：2010-06-08
申请号：US12019511
申请日：2008-01-24
申请人： Mitiko Miura , Noriaki Nakayama
发明人： Mitiko Miura , Noriaki Nakayama
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： There is disclosed a simulation model and method for designing a semiconductor device being used for a simulation apparatus for designing a semiconductor device that includes using assuming units as to carrier transient density and current flow of electrodes along with a non-quasi-static model describing unit of the simulation apparatus. A simulation apparatus and computer readable medium with a simulation program for executing the method are also included.
摘要翻译：公开了一种用于设计半导体器件的模拟模型和方法，该半导体器件用于设计半导体器件，该半导体器件包括使用假设单元对电极的载流子瞬时密度和电流以及非准静态模型描述单元的模拟装置。还包括具有用于执行该方法的仿真程序的模拟装置和计算机可读介质。

4. 发明申请

US20090070084A1 SIMULATION METHOD AND SIMULATION APPARATUS FOR LDMOSFET 失效
标题翻译： LDMOSFET的仿真方法和仿真设备
公开(公告)号：US20090070084A1
公开(公告)日：2009-03-12
申请号：US12130320
申请日：2008-05-30
申请人： Mitiko Miura , Masahiro Yokomichi , Takahiro Kajiwara , Norio Sadachika , Masataka Miyake , Takahiro Iizuka , Masahiko Taguchi , Tatsuya Ohguro
发明人： Mitiko Miura , Masahiro Yokomichi , Takahiro Kajiwara , Norio Sadachika , Masataka Miyake , Takahiro Iizuka , Masahiko Taguchi , Tatsuya Ohguro
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The drift region for increasing the breakdown voltage in an LDMOSFET is regarded as a resistive element. The potential distribution of the overall device is calculated by obtaining a potential distribution considering the resistance by iterative calculation. A capacitance generated in the drift region is analytically calculated assuming a linear potential distribution. A capacitance generated in the overlap region between the gate electrode and the drift region is calculated by considering the potential from the depletion region to the accumulation region.
摘要翻译：用于增加LDMOSFET中的击穿电压的漂移区域被认为是电阻元件。通过迭代计算考虑电阻的电位分布来计算整个装置的电位分布。假设线性电位分布，分析地计算在漂移区域中产生的电容。通过考虑从耗尽区域到累积区域的电位来计算在栅电极和漂移区域之间的重叠区域中产生的电容。

5. 发明申请

US20050120315A1 Simulation model for designing semiconductor devices, apparatus for simulating the designing of semiconductor devices, method of simulating the designing of semiconductor devices, computer-readable recording medium storing a program for simulating the designing of semiconductor devices, semiconductor device, and method of manufacturing the semiconductor device 失效
标题翻译：用于设计半导体器件的模拟模型，用于模拟半导体器件的设计的装置，模拟半导体器件的设计的方法，存储用于模拟半导体器件的设计的程序的计算机可读记录介质，半导体器件和制造半导体的方法设备
公开(公告)号：US20050120315A1
公开(公告)日：2005-06-02
申请号：US10933335
申请日：2004-09-03
申请人： Mitiko Miura , Noriaki Nakayama
发明人： Mitiko Miura , Noriaki Nakayama
IPC分类号： G06F17/50 , H01L21/00 , H01L21/336 , H01L21/82 , H01L29/00 , H01L29/78
CPC分类号： G06F17/5036
摘要： There is disclosed a simulation model for designing a semiconductor device, comprising adding at least a part of a difference between a density of a carrier described in a quasi-static manner with respect to a voltage applied between electrodes at a first time and a density of the carrier described in a transient state at a second time before the first time to the carrier density at the second time in accordance with a running delay of the carrier between both the times to thereby describe the carrier density at the first time in the transient state with respect to a semiconductor element having the first and second electrodes. A current flowing between the electrodes is described as a sum of a current flowing between the electrodes in the quasi-static manner, and a displacement current between the electrodes.
摘要翻译：公开了一种用于设计半导体器件的仿真模型，包括：以准静态方式描述的载流子的密度相对于在第一时间施加在电极之间的电压和至少一个载波在第一时间之前的第二时间根据两个时间之间的载波的运行延迟在第二时间处于暂态状态下描述为载波密度，从而描述在瞬时状态下的第一时间的载波密度相对于具有第一和第二电极的半导体元件。在电极之间流动的电流被描述为以静态方式在电极之间流动的电流和电极之间的位移电流之和。

6. 发明授权

US07983889B2 Simulation method and simulation apparatus for LDMOSFET 失效
标题翻译： LDMOSFET的仿真方法和仿真装置
公开(公告)号：US07983889B2
公开(公告)日：2011-07-19
申请号：US12130320
申请日：2008-05-30
申请人： Mitiko Miura , Masahiro Yokomichi , Takahiro Kajiwara , Norio Sadachika , Masataka Miyake , Takahiro Iizuka , Masahiko Taguchi , Tatsuya Ohguro
发明人： Mitiko Miura , Masahiro Yokomichi , Takahiro Kajiwara , Norio Sadachika , Masataka Miyake , Takahiro Iizuka , Masahiko Taguchi , Tatsuya Ohguro
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The drift region for increasing the breakdown voltage in an LDMOSFET is regarded as a resistive element. The potential distribution of the overall device is calculated by obtaining a potential distribution considering the resistance by iterative calculation. A capacitance generated in the drift region is analytically calculated assuming a linear potential distribution. A capacitance generated in the overlap region between the gate electrode and the drift region is calculated by considering the potential from the depletion region to the accumulation region.
摘要翻译：用于增加LDMOSFET中的击穿电压的漂移区域被认为是电阻元件。通过迭代计算考虑电阻的电位分布来计算整个装置的电位分布。假设线性电位分布，分析地计算在漂移区域中产生的电容。通过考虑从耗尽区域到累积区域的电位来计算在栅电极和漂移区域之间的重叠区域中产生的电容。

7. 发明授权

US07343571B2 Simulation model for a semiconductor device describing a quasi-static density of a carrier as a non-quasi-static model 失效
标题翻译：用于描述作为非准静态模型的载波的准静态密度的半导体器件的仿真模型
公开(公告)号：US07343571B2
公开(公告)日：2008-03-11
申请号：US10933335
申请日：2004-09-03
申请人： Mitiko Miura , Noriaki Nakayama
发明人： Mitiko Miura , Noriaki Nakayama
IPC分类号： G06F17/59 , H03K17/693 , G01R31/26
CPC分类号： G06F17/5036
摘要： There is disclosed a simulation model for designing a semiconductor device, comprising adding at least a part of a difference between a density of a carrier described in a quasi-static manner with respect to a voltage applied between electrodes at a first time and a density of the carrier described in a transient state at a second time before the first time to the carrier density at the second time in accordance with a running delay of the carrier between both the times to thereby describe the carrier density at the first time in the transient state with respect to a semiconductor element having the first and second electrodes. A current flowing between the electrodes is described as a sum of a current flowing between the electrodes in the quasi-static manner, and a displacement current between the electrodes.
摘要翻译：公开了一种用于设计半导体器件的仿真模型，包括：以准静态方式描述的载流子的密度相对于在第一时间施加在电极之间的电压和至少一个载波在第一时间之前的第二时间根据两个时间之间的载波的运行延迟在第二时间处于暂态状态下描述为载波密度，从而描述在瞬时状态下的第一时间的载波密度相对于具有第一和第二电极的半导体元件。在电极之间流动的电流被描述为以静态方式在电极之间流动的电流和电极之间的位移电流之和。

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