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1. 发明授权

US06613190B2 Method of and apparatus for manufacturing tantalum solid electrolytic capacitors 有权
公开(公告)号：US06613190B2
公开(公告)日：2003-09-02
申请号：US10162574
申请日：2002-06-06
申请人： Minoru Omori , Yoshitsugu Uenishi , Osamu Tomita , Nario Kawakita , Masakuni Ogino , Yoji Masuda , Tsuyoshi Yoshino
发明人： Minoru Omori , Yoshitsugu Uenishi , Osamu Tomita , Nario Kawakita , Masakuni Ogino , Yoji Masuda , Tsuyoshi Yoshino
IPC分类号： B30B1534
CPC分类号： H01G9/012 , Y10T29/41 , Y10T29/413 , Y10T29/417
摘要： A length of metallic lead from having anode terminals and cathode terminals integrally formed with each other extends between upper and lower molds of an apparatus for manufacturing tantalum solid electrolytic capacitors. The cathode terminals are first coated with a thermosetting conductive adhesive, and cathode layers of capacitor elements are then placed on the conductive adhesive. Thereafter, anode leads extending outwardly from the capacitor elements are placed on the anode terminals are joined thereto, respectively, by welding. A pressure is applied to the capacitor elements so that a portion of the conductive adhesive is squeezed out from one surface of each of the plurality of capacitor elements to a neighboring side surface thereof. The cathode terminals are then joined to the capacitor elements, respectively, by heat-curing the conductive adhesive, and the capacitor elements are finally covered with a sheathing resin.

2. 发明授权

US06423104B1 Method of and apparatus for manufacturing tantalum solid electrolytic capacitors 有权
标题翻译：钽固体电解电容器的制造方法和设备
公开(公告)号：US06423104B1
公开(公告)日：2002-07-23
申请号：US09712158
申请日：2000-11-15
申请人： Minoru Omori , Yoshitsugu Uenishi , Osamu Tomita , Nario Kawakita , Masakuni Ogino , Yoji Masuda , Tsuyoshi Yoshino
发明人： Minoru Omori , Yoshitsugu Uenishi , Osamu Tomita , Nario Kawakita , Masakuni Ogino , Yoji Masuda , Tsuyoshi Yoshino
IPC分类号： H01G900
CPC分类号： H01G9/012 , Y10T29/41 , Y10T29/413 , Y10T29/417
摘要： A length of metallic lead from having anode terminals and cathode terminals integrally formed with each other extends between upper and lower molds of an apparatus for manufacturing tantalum solid electrolytic capacitors. The cathode terminals are first coated with a thermosetting conductive adhesive, and cathode layers of capacitor elements are then placed on the conductive adhesive. Thereafter, anode leads extending outwardly from the capacitor elements are placed on the anode terminals are joined thereto, respectively, by welding. A pressure is applied to the capacitor elements so that a portion of the conductive adhesive is squeezed out from one surface of each of the plurality of capacitor elements to a neighboring side surface thereof The cathode terminals are then joined to the capacitor elements, respectively, by heat-curing the conductive adhesive, and the capacitor elements are finally covered with a sheathing resin.
摘要翻译：具有彼此一体形成的阳极端子和阴极端子的金属引线的长度在用于制造钽固体电解电容器的设备的上模和下模之间延伸。阴极端子首先涂覆有热固性导电粘合剂，然后将电容器元件的阴极层放置在导电粘合剂上。此后，分别通过焊接将放置在阳极端子上的从电容器元件向外延伸的阳极引线连接到阳极端子上。对电容器元件施加压力，使得导电粘合剂的一部分从多个电容器元件的每一个的一个表面挤出到其相邻的侧表面。然后，阴极端子分别通过热固化导电粘合剂，电容器元件最后用护套树脂覆盖。

3. 发明授权

US06400556B1 Solid electrolytic capacitor and method of fabricating the same 有权
标题翻译：固体电解电容器及其制造方法
公开(公告)号：US06400556B1
公开(公告)日：2002-06-04
申请号：US09658666
申请日：2000-09-08
申请人： Yoji Masuda , Tsuyoshi Yoshino
发明人： Yoji Masuda , Tsuyoshi Yoshino
IPC分类号： H01G900
CPC分类号： H01G9/15
摘要： A solid electrolytic capacitor minimized in both equivalent serial resistance (ESR) and equivalent serial inductance (ESI) by eliminating redundant space created by its electrode is presented. The solid electrolytic capacitor includes a capacitor element including mainly of a positive electrode body, having a positive electrode lead embedded therein, and made of any form of a valve metal, such as a net, a sheet, a foil, and modifications thereof with a rough surface; a positive electrode terminal connected to the positive electrode lead; a negative electrode terminal connected to a negative electrode layer; and a housing resin coated by molding. This improves the installation efficiency of the capacitor element, and contributes to the small, thin structure of the solid electrolytic capacitor.
摘要翻译：介绍了通过消除其电极产生的冗余空间，使等效串联电阻（ESR）和等效串联电感（ESI）最小化的固体电解电容器。固体电解电容器包括主要包括正电极体的电容器元件，其具有嵌入其中的正电极引线，并且由任何形式的阀金属制成，例如网，片，箔，及其变型，其具有粗糙的表面; 与正极引线连接的正极端子; 连接到负极层的负极端子; 和通过模制涂覆的外壳树脂。这提高了电容元件的安装效率，有助于固体电解电容器的薄型结构。

4. 发明申请

US20060242503A1 Integrated circuit test system 失效
公开(公告)号：US20060242503A1
公开(公告)日：2006-10-26
申请号：US11407928
申请日：2006-04-21
申请人： Yoji Masuda
发明人： Yoji Masuda
IPC分类号： G01R31/28
CPC分类号： G01R31/31921
摘要： A test pattern compressed by an algorithm allowing real-time expansion of data corresponding to each of pins of an LSI is stored in a pattern memory of a pattern generator. A frame processor executes a predetermined program to perform expansion of a test pattern output by the pattern generator by software, generates, based on expanded data, a pulse waveform, and outputs the generated pulse waveform.

5. 发明授权

US07266485B2 Method for making equivalent circuit model of passive element, simulator, and storage medium 有权
标题翻译：无源元件，模拟器和存储介质等效电路模型的制作方法
公开(公告)号：US07266485B2
公开(公告)日：2007-09-04
申请号：US10258700
申请日：2002-02-20
申请人： Hiroyuki Maeshima , Yoichi Aoshima , Yasuhiro Kobatake , Yoji Masuda , Mamoru Ito
发明人： Hiroyuki Maeshima , Yoichi Aoshima , Yasuhiro Kobatake , Yoji Masuda , Mamoru Ito
IPC分类号： G06F17/50 , G01R25/00
CPC分类号： G06F17/5036
摘要： A method of deriving an equivalent circuit model for a passive component includes a first step of providing a given frequency characteristic of a capacitor, a second step of forming one of an RC circuit, an RL circuit, and an RCL circuit using frequency-independent resistances (R), capacitances (C) and/or inductances (L), as the equivalent circuit model representing a circuit capable of performing a simulation in a time domain, a third step of composing an evaluation function for evaluating accuracy of the equivalent circuit model formed in the second step, and a fourth step of determining values of the circuit components by minimizing the evaluation function composed in the third step. The method with a simulator adapted for implementing this method and a computer-readable storage medium containing a recorded program, derives the equivalent circuit model for a capacitor. The model is capable of performing a simulation in the time domain using a common procedure not dependent upon types of passive components.
摘要翻译：导出无源部件的等效电路模型的方法包括提供电容器的给定频率特性的第一步骤，使用频率独立电阻形成RC电路，RL电路和RCL电路之一的第二步骤（R），电容（C）和/或电感（L），作为表示能够在时域中进行模拟的电路的等效电路模型，构成用于评估等效电路模型的精度的评估函数的第三步骤以及第四步骤，通过使在第三步骤中组成的评估函数最小化来确定电路部件的值。具有用于实现该方法的模拟器的方法和包含记录的程序的计算机可读存储介质，导出电容器的等效电路模型。该模型能够使用不依赖于无源组件类型的常用过程在时域中执行模拟。

6. 发明授权

US07516381B2 Integrated circuit test system 失效
标题翻译：集成电路测试系统
公开(公告)号：US07516381B2
公开(公告)日：2009-04-07
申请号：US11407928
申请日：2006-04-21
申请人： Yoji Masuda
发明人： Yoji Masuda
IPC分类号： G01R31/28
CPC分类号： G01R31/31921
摘要： A test pattern compressed by an algorithm allowing real-time expansion of data corresponding to each of pins of an LSI is stored in a pattern memory of a pattern generator. A frame processor executes a predetermined program to perform expansion of a test pattern output by the pattern generator by software, generates, based on expanded data, a pulse waveform, and outputs the generated pulse waveform.
摘要翻译：通过允许对应于LSI的每个引脚的数据的实时扩展的算法压缩的测试图案被存储在模式发生器的模式存储器中。帧处理器执行预定程序以通过软件执行由模式发生器输出的测试模式的扩展，基于扩展数据生成脉冲波形，并输出所生成的脉冲波形。

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