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1. 发明授权

US06583051B2 Method of manufacturing an amorphized barrier layer for integrated circuit interconnects 失效
公开(公告)号：US06583051B2
公开(公告)日：2003-06-24
申请号：US09989972
申请日：2001-11-20
申请人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
发明人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

2. 发明授权

US06348732B1 Amorphized barrier layer for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的非晶化阻挡层
公开(公告)号：US06348732B1
公开(公告)日：2002-02-19
申请号：US09715702
申请日：2000-11-18
申请人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
发明人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。非晶化的阻挡层对开口进行排列，并且沉积种子层以使非晶化的阻挡层排列。导体芯填充阻挡层上的开口以形成导体通道。种子层牢固地结合到非晶化阻挡层并防止沿种子和阻挡层之间的表面的电迁移。

3. 发明授权

US06504251B1 Heat/cold amorphized barrier layer for integrated circuit interconnects 失效
标题翻译：用于集成电路互连的热/冷非晶形阻挡层
公开(公告)号：US06504251B1
公开(公告)日：2003-01-07
申请号：US09715616
申请日：2000-11-18
申请人： Minh Quoc Tran , Sergey D. Lopatin , Minh Van Ngo
发明人： Minh Quoc Tran , Sergey D. Lopatin , Minh Van Ngo
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76873
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening. An amorphized layer is formed by rapid heating of the barrier layer and rapid cooling of the semiconductor substrate. A seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。屏障层划线开口。通过阻挡层的快速加热和半导体衬底的快速冷却来形成非晶化层。沉积种子层以排列非晶化阻挡层。导体芯填充阻挡层上的开口以形成导体通道。种子层牢固地结合到非晶化阻挡层。

4. 发明授权

US06501177B1 Atomic layer barrier layer for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的原子层阻挡层
公开(公告)号：US06501177B1
公开(公告)日：2002-12-31
申请号：US09678946
申请日：2000-10-03
申请人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
发明人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
IPC分类号： H01L2448
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76856 , H01L21/76873
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening and has a first amorphized atomic layer of a barrier compound and a second atomic layer of a barrier metal. A seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。阻挡层对开口进行排列，并且具有阻挡化合物的第一非晶化原子层和阻挡金属的第二原子层。沉积种子层以排列非晶化阻挡层。导体芯填充阻挡层上的开口以形成导体通道。种子层牢固地结合到非晶化阻挡层并防止沿种子和阻挡层之间的表面的电迁移。

5. 发明授权

US06770905B1 Implantation for the formation of CuX layer in an organic memory device 失效
标题翻译：用于在有机存储器件中形成CuX层的植入
公开(公告)号：US06770905B1
公开(公告)日：2004-08-03
申请号：US10314054
申请日：2002-12-05
申请人： Matthew S. Buynoski , Suzette K. Pangrle , Sergey D. Lopatin , Minh Van Ngo
发明人： Matthew S. Buynoski , Suzette K. Pangrle , Sergey D. Lopatin , Minh Van Ngo
IPC分类号： H01L2940
CPC分类号： H01L51/0037 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0043 , H01L51/0046 , H01L51/0048 , H01L51/0052 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： An organic memory cell having a CuX layer made by implantation is disclosed. The organic memory cell is made of two electrodes, at least one containing copper, with a controllably conductive media between the two electrodes. The controllably conductive media contains an organic semiconductor layer and CuX layer made by implantation of a Group VIB element.
摘要翻译：公开了一种具有通过注入制造的CuX层的有机存储单元。有机存储单元由两个电极组成，至少一个电极含有铜，两个电极之间具有可控导电介质。可控导电介质包含通过注入VIB族元素制成的有机半导体层和CuX层。

6. 发明授权

US07323418B1 Etch-back process for capping a polymer memory device 有权
标题翻译：用于封盖聚合物存储器件的蚀刻工艺
公开(公告)号：US07323418B1
公开(公告)日：2008-01-29
申请号：US11102004
申请日：2005-04-08
申请人： Minh Van Ngo , Angela T. Hui , Sergey D. Lopatin
发明人： Minh Van Ngo , Angela T. Hui , Sergey D. Lopatin
IPC分类号： H01L21/302
CPC分类号： G11C13/0016 , G11C13/0014 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/1608 , H01L45/1683 , H01L51/0591
摘要： The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.
摘要翻译：本发明利用回蚀工艺来提供用于聚合物存储元件的电极帽。这允许聚合物存储元件形成在嵌入在衬底上形成的层中的通孔内。通过利用回蚀工艺，本发明提供了利用通孔的聚合物存储器件的适当功能所需的微小电触点。在本发明的一个实例中，在电介质层中形成一个或多个通孔以露出下层。然后在下层上的通孔内形成聚合物层，其中沉积在聚合物层上的顶部电极材料层填充通孔的剩余部分。然后通过蚀刻工艺去除顶部电极材料的多余部分以形成提供聚合物存储元件的电接触点的电极帽。

7. 发明授权

US06787458B1 Polymer memory device formed in via opening 失效
标题翻译：聚合物存储器件形成在通孔中
公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

8. 发明授权

US06836398B1 System and method of forming a passive layer by a CMP process 有权
标题翻译：通过CMP工艺形成钝化层的系统和方法
公开(公告)号：US06836398B1
公开(公告)日：2004-12-28
申请号：US10284769
申请日：2002-10-31
申请人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
发明人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
IPC分类号： H01G435
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L21/3212 , H01L27/285 , H01L28/75
摘要： The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.
摘要翻译：本发明提供了通过平坦化工艺有助于形成半导体器件的系统和方法。本发明利用通常在化学机械平面化（CMP）工艺中发生的凹陷效应。在半导体器件上进行还原CMP工艺以形成无源层，而不是执行第一CMP，随后进行沉积和第二CMP以形成钝化层。还原CMP方法利用包含在电极的盘区域中形成钝化层的还原化学物质的浆料。因此，钝化层与用于形成电极的还原CMP工艺结合形成。

9. 发明授权

US06900488B1 Multi-cell organic memory element and methods of operating and fabricating 有权
标题翻译：多单元有机存储元件及其操作和制造方法
公开(公告)号：US06900488B1
公开(公告)日：2005-05-31
申请号：US10284946
申请日：2002-10-31
申请人： Sergey D. Lopatin , Mark S. Chang , Minh Van Ngo , Patrick K. Cheung
发明人： Sergey D. Lopatin , Mark S. Chang , Minh Van Ngo , Patrick K. Cheung
IPC分类号： H01L27/28 , H01L51/00 , H01L51/30 , H01L51/40 , H01L29/76
CPC分类号： H01L27/285 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0021 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0078
摘要： The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of the lower electrode. An Inter Layer Dielectric (ILD) is formed above the passive layers and lower electrode, whereby a via or other type relief is created within the ILD and an organic semiconductor material is then utilized to partially fill the via above the passive layer. The portions of the via that are not filled with organic material are filled with dielectric material, thus forming a multi-dimensional memory structure above the passive layer or layers and the lower electrode. One or more top electrodes are then added above the memory structure, whereby distinctive memory cells are created within the organic portions of the memory structure and activated (e.g., read/write) between the top electrodes and bottom electrode, respectively. In this manner, multiple storage cells can be formed within a singular organic structure thereby increasing memory device density and storage.
摘要翻译：本发明提供一种多小区有机存储装置，其可以作为具有构造在存储装置内的多个多小区结构的非易失性存储装置来操作。可以形成下电极，其中在下电极的顶部上形成一个或多个钝化层。在无源层和下电极之上形成层间电介质（ILD），由此在ILD内产生通孔或其它类型的浮雕，然后利用有机半导体材料部分地填充钝化层以上的通孔。通孔中没有填充有机材料的部分用电介质材料填充，从而在钝化层或下层电极之上形成多维存储结构。然后在存储器结构上方添加一个或多个顶部电极，由此在存储器结构的有机部分内分别创建独特的存储单元，并分别在顶部电极和底部电极之间激活（例如，读取/写入）。以这种方式，可以在单个有机结构内形成多个存储单元，从而增加存储器件密度和存储。

10. 发明授权

US06773954B1 Methods of forming passive layers in organic memory cells 失效
标题翻译：在有机记忆细胞中形成钝化层的方法
公开(公告)号：US06773954B1
公开(公告)日：2004-08-10
申请号：US10313494
申请日：2002-12-05
申请人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
发明人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
IPC分类号： H01L5140
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L27/28 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0043 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode and adjacent passive layer are described.
摘要翻译：公开了在两个电极之间制造由具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含有机半导体层和无源层。特别地，描述了形成电极和相邻钝化层的新颖方法。

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