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    • 1. 发明申请
    • CATALYST COMPOSITION FOR OLIGOMERIZATION OF ETHYLENE AND PROCESSES OF OLIGOMERIZATION
    • 乙烯低聚化催化剂组合物及其低分子化方法
    • US20130018214A1
    • 2013-01-17
    • US13637976
    • 2011-03-30
    • Mingfang ZhengWeizhen LiHuaijie WangJun LiuHaiying ZhangYu ZhouTonglin LiLan ZhaoJilong WangHongfei WuYuling PiaoJunlong Sui
    • Mingfang ZhengWeizhen LiHuaijie WangJun LiuHaiying ZhangYu ZhouTonglin LiLan ZhaoJilong WangHongfei WuYuling PiaoJunlong Sui
    • B01J31/12C07C2/26
    • C08F10/02B01J31/143B01J31/183B01J2231/20B01J2531/842B01J2531/845B01J2531/847C07C2/32C07C2531/14C07C2531/22C08F110/02Y02P20/52C08F4/7042C08F2500/02C07C11/02C08F210/02
    • The present invention provides a catalyst composition for the ethylene oligomerization, which comprises 2-imino-1,10-phenanthroline coordinated iron (II), cobalt (II) or nickel (II) chloride as main catalyst and triethylaluminum as cocatalyst. The present invention also provides a process for oligomerization of ethylene is provided, wherein a catalyst composition comprising 2-imino-1,10-phenanthroline coordinated iron (II), cobalt (II) or nickel (II) chloride as main catalyst and triethylaluminum as cocatalyst is used, and the molar ratio of aluminum in the cocatalyst to central metal in the main catalyst ranges from 30 to less than 200. According to the present invention, another process for oligomerization of ethylene is also provided, wherein a catalyst composition comprising 2-imino-1,10-phenanthroline coordinated iron (II), cobalt (II) or nickel (II) chloride as main catalyst and triethylaluminum as cocatalyst is used, and the temperature of ethylene oligomerization ranges from −10 to 19° C. According to the present invention, the price of cocatalyst i.e. triethylaluminum, is low, just a fraction of that of methylaluminoxane, the amount of cocatalyst is therefore significantly reduced, with the catalytic activity is still acceptable, thus the cost of ethylene oligomerization is significantly reduced. In view of both the catalytic activity and the cost, the present invention is highly applicable in industry.
    • 本发明提供了一种用于乙烯低聚的催化剂组合物,其包含2-亚氨基-1,10-菲咯啉配位的铁(II),钴(II)或氯化镍(II)作为主要催化剂,三乙基铝作为助催化剂。 本发明还提供了一种乙烯低聚方法,其中包含2-亚氨基-1,10-菲咯啉配位的铁(II),钴(II)或氯化镍(II)作为主要催化剂的催化剂组合物和三乙基铝作为 助催化剂,主催化剂中助催化剂与中心金属之间的铝的摩尔比为30至小于200.根据本发明,还提供了另一种乙烯低聚方法,其中催化剂组合物包含2 - 亚氨基-1,10-菲咯啉配位的铁(II),钴(II)或氯化镍(II)为主催化剂,三乙基铝为助催化剂,乙烯齐聚温度为-10〜19℃。 对于本发明,助催化剂即三乙基铝的价格低,仅仅是甲基铝氧烷的一部分,因此助催化剂的量显着降低,催化活性为 仍然是可接受的,因此乙烯低聚的成本显着降低。 鉴于催化活性和成本两方面,本发明在工业上是高度适用的。
    • 6. 发明授权
    • Preparation method of phenylcarboxamides
    • 苯甲酰胺的制备方法
    • US08217179B2
    • 2012-07-10
    • US12918133
    • 2009-03-30
    • Bin LiHongfei WuHaibo YuHuibin Yang
    • Bin LiHongfei WuHaibo YuHuibin Yang
    • C07D401/04
    • C07D401/04
    • A preparation method of phenylcarboxamides of formula (I), the reaction scheme of which is as follows: wherein the groups are defined in the description. In this method, 3-halo-1-(3-chloro-2-pyridinyl)-4,5-dihydro-1H-pyrazole-5-carboxylic acid esters (V) as the raw materials are hydrolyzed to obtain carboxylic acids of formula (IV) under a basic condition, and carboxylic acids (IV) are simultaneously acyl halogenated and oxidated to get acyl halide of formula (III), and then without the presence of a acid binging agent, acyl chlorides (III) are reacted with substituted anilines (II) to get phenylcarboxamides of formula (I) in high yield.
    • 式(I)的苯甲酰胺的制备方法,其反应方案如下:其中这些基团在说明书中定义。 在该方法中,将作为原料的3-卤代-1-(3-氯-2-吡啶基)-4,5-二氢-1H-吡唑-5-羧酸酯(V)水解,得到式 (Ⅳ),羧酸(Ⅳ)同时进行酰基卤化和氧化,得到式(Ⅳ)的酰卤,然后不存在酸性起始剂,酰基氯(III)与取代的 苯胺(II)以高产率得到式(I)的苯基甲酰胺。
    • 8. 发明申请
    • PERFORMANCE INVERSION DETECTION CIRCUIT AND A DESIGN STRUCTURE FOR THE SAME
    • 性能反相检测电路及其设计结构
    • US20090179670A1
    • 2009-07-16
    • US12014430
    • 2008-01-15
    • Albert M. ChuJohn A. FifieldDaryl M. SeitzerHongfei Wu
    • Albert M. ChuJohn A. FifieldDaryl M. SeitzerHongfei Wu
    • H03F3/45
    • H03F3/45475H03F2200/447H03F2203/45586H03F2203/45618H03F2203/45622
    • A circuit containing a parallel connection of a first sub-circuit and a second sub-circuit is provided. The first sub-circuit comprises a serial connection of a first field effect transistor having a first threshold voltage and a first voltage dividing device. The second sub-circuit comprises a serial connection of a second field effect transistor having a second threshold voltage, which is different from the first threshold voltage, and a second voltage dividing device. The voltage between the first field effect transistor and the first voltage dividing device is compared with the voltage between the second field effect transistor and the second voltage dividing device so that a signal may be generated at a temperature at which the ratio of a performance parameter such as on-current between the first and second field effect transistors crosses over a predefined value. The signal may be advantageously employed to actively control circuit characteristics.
    • 提供了包含第一子电路和第二子电路的并联连接的电路。 第一子电路包括具有第一阈值电压的第一场效应晶体管和第一分压装置的串联连接。 第二子电路包括具有与第一阈值电压不同的第二阈值电压的第二场效应晶体管的串联连接和第二分压装置。 将第一场效应晶体管和第一分压装置之间的电压与第二场效应晶体管和第二分压装置之间的电压进行比较,使得可以在这样的温度下产生信号, 因为第一和第二场效应晶体管之间的导通电流跨越预定值。 可以有利地使用该信号来主动地控制电路特性。
    • 10. 发明申请
    • STROBE RECEIVER WITH DIGITAL HIGH-HIGH PROTECT
    • 具有数字高保护功能的接收器
    • US20070159225A1
    • 2007-07-12
    • US11275537
    • 2006-01-12
    • William BucossiHongfei Wu
    • William BucossiHongfei Wu
    • G06F1/04
    • G06F1/04
    • A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.
    • 数字时钟产生电路(及其操作方法)。 数字时钟产生电路包括第一,第二,第三差分比较器电路。 第一差分比较器电路接收正差分时钟信号和参考电压,并产生第一输出信号。 第二差分比较器电路接收正和负差分时钟信号,并产生第二输出信号。 第三差分比较器电路接收参考电压和负差分时钟信号,并产生第三输出信号。 高电平检测电路接收第一输出信号和第三输出信号,并产生使能信号。 数字时钟发生电路还包括接收第二输出信号的锁存电路和使能信号并产生数字时钟信号。 锁存电路包括具有毛刺或抗噪声的锁存器。