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1. 发明授权

US07968967B2 One-time-programmable anti-fuse formed using damascene process 有权
标题翻译：使用镶嵌工艺形成一次性可编程反熔丝
公开(公告)号：US07968967B2
公开(公告)日：2011-06-28
申请号：US11487849
申请日：2006-07-17
申请人： Ming-Tsong Wang , Tong-Chern Ong
发明人： Ming-Tsong Wang , Tong-Chern Ong
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power source. The stacked structure includes a bottom electrode, a top electrode, and an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer has a breakdown voltage lower than a pre-determined write voltage provided by the power source and higher than a pre-determined read voltage provided by the power source.
摘要翻译：半导体结构包括在半导体衬底上的半导体衬底，电源和层叠结构，并且耦合到电源。堆叠结构包括底部电极，顶部电极和顶部电极和底部电极之间的绝缘层，其中绝缘层具有低于由电源提供的预定写入电压的击穿电压，并且高于由电源提供的预定读取电压。

2. 发明申请

US20100001335A1 Flash Memory Cells Having Leakage-Inhibition Layers 有权
标题翻译：具有泄漏抑制层的闪存单元
公开(公告)号：US20100001335A1
公开(公告)日：2010-01-07
申请号：US12168545
申请日：2008-07-07
申请人： Ming-Tsong Wang , Tong-Chern Ong , Albert Chin , Hsueh-Jen Yang
发明人： Ming-Tsong Wang , Tong-Chern Ong , Albert Chin , Hsueh-Jen Yang
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L29/513 , H01L29/518
摘要： A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.
摘要翻译：半导体器件包括半导体衬底; 在所述半导体衬底上的隧道层，其中所述隧道层具有第一导带; 在所述隧道层上的存储层，其中所述存储层具有第二导带; 在所述存储层上的阻挡层，其中所述阻挡层具有第三导带; 阻挡层上的栅电极; 以及第一泄漏抑制层和第二泄漏抑制层中的至少一个。第一泄漏抑制层在隧道层和存储层之间，并且具有比第一导带低的第四导带。第二泄漏抑制层位于阻挡层和栅电极之间，并且具有比第三导带低的第五导带。

3. 发明申请

US20070272916A1 Flash memory with deep quantum well and high-K dielectric 有权
标题翻译：具有深量子阱和高K电介质的闪存
公开(公告)号：US20070272916A1
公开(公告)日：2007-11-29
申请号：US11440667
申请日：2006-05-25
申请人： Ming-Tsong Wang , Tong-Chern Ong , Albert Chin , Chun-Hung Lai
发明人： Ming-Tsong Wang , Tong-Chern Ong , Albert Chin , Chun-Hung Lai
IPC分类号： H01L29/06
CPC分类号： H01L29/792 , H01L29/517 , H01L29/66833
摘要： A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably has a conduction band lower than a conduction band of silicon. The blocking layer is preferably formed of a high-k dielectric material.
摘要翻译：闪存单元包括形成在基板上的基板和栅极结构。栅极结构包括在衬底上的隧道层，隧道层上的存储层，存储层上的阻挡层和电介质上的栅电极。存储层优选具有比硅的导带低的导带。阻挡层优选由高k电介质材料形成。

4. 发明授权

US08735963B2 Flash memory cells having leakage-inhibition layers 有权
标题翻译：具有泄漏抑制层的闪存单元
公开(公告)号：US08735963B2
公开(公告)日：2014-05-27
申请号：US12168545
申请日：2008-07-07
申请人： Ming-Tsong Wang , Tong-Chern Ong , Albert Chin , Hsueh-Jen Yang
发明人： Ming-Tsong Wang , Tong-Chern Ong , Albert Chin , Hsueh-Jen Yang
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L29/513 , H01L29/518
摘要： A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.
摘要翻译：半导体器件包括半导体衬底; 在所述半导体衬底上的隧道层，其中所述隧道层具有第一导带; 在所述隧道层上的存储层，其中所述存储层具有第二导带; 在所述存储层上的阻挡层，其中所述阻挡层具有第三导带; 阻挡层上的栅电极; 以及第一泄漏抑制层和第二泄漏抑制层中的至少一个。第一泄漏抑制层在隧道层和存储层之间，并且具有比第一导带低的第四导带。第二泄漏抑制层位于阻挡层和栅电极之间，并且具有比第三导带低的第五导带。

5. 发明授权

US08294197B2 Program/erase schemes for floating gate memory cells 有权
标题翻译：浮动栅极存储单元的编程/擦除方案
公开(公告)号：US08294197B2
公开(公告)日：2012-10-23
申请号：US11525351
申请日：2006-09-22
申请人： Ming-Tsong Wang , Tong-Chern Ong
发明人： Ming-Tsong Wang , Tong-Chern Ong
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/7883 , H01L29/7884
摘要： A flash memory cell includes a substrate, a blocking layer over the substrate, a floating gate over the blocking layer, a retention layer over the floating gate, a control gate over the retention layer, a tunneling layer over the control gate, a top gate over the tunneling layer, and a voltage source electrically coupled between the top gate and the control gate. Various charge tunneling mechanisms may be used for charges to tunnel through the retention layer.
摘要翻译：闪存单元包括衬底，衬底上的阻挡层，阻挡层上的浮动栅极，浮置栅极上的保持层，保持层上的控制栅极，控制栅极上的隧道层，顶栅极以及电耦合在顶栅和控制栅之间的电压源。可以使用各种电荷隧穿机构用于穿过保留层的电荷。

6. 发明申请

US20080073689A1 Program/erase schemes for floating gate memory cells 有权
标题翻译：浮动栅极存储单元的编程/擦除方案
公开(公告)号：US20080073689A1
公开(公告)日：2008-03-27
申请号：US11525351
申请日：2006-09-22
申请人： Ming-Tsong Wang , Tong-Chern Ong
发明人： Ming-Tsong Wang , Tong-Chern Ong
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/7883 , H01L29/7884
摘要： A flash memory cell includes a substrate, a blocking layer over the substrate, a floating gate over the blocking layer, a retention layer over the floating gate, a control gate over the retention layer, a tunneling layer over the control gate, a top gate over the tunneling layer, and a voltage source electrically coupled between the top gate and the control gate. Various charge tunneling mechanisms may be used for charges to tunnel through the retention layer.
摘要翻译：闪存单元包括衬底，衬底上的阻挡层，阻挡层上的浮动栅极，浮置栅极上的保持层，保持层上的控制栅极，控制栅极上的隧道层，顶栅极以及电耦合在顶栅和控制栅之间的电压源。可以使用各种电荷隧穿机构用于穿过保留层的电荷。

7. 发明授权

US08816422B2 Multi-trapping layer flash memory cell 有权
标题翻译：多陷阱层闪存单元
公开(公告)号：US08816422B2
公开(公告)日：2014-08-26
申请号：US11521805
申请日：2006-09-15
申请人： Ming-Tsong Wang , Tong-Chern Ong
发明人： Ming-Tsong Wang , Tong-Chern Ong
IPC分类号： H01L29/788 , H01L29/792 , H01L29/423 , H01L21/28 , G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： H01L29/42348 , G11C11/5671 , G11C16/0466 , G11C16/10 , H01L21/28273 , H01L21/28282 , H01L29/7887 , H01L29/7923
摘要： A semiconductor device includes a semiconductor substrate, a top gate over the semiconductor substrate, and a stacked gate between the top gate and the semiconductor substrate. The stacked gate includes a first tunneling layer, a first storage layer adjoining the first tunneling layer, and an additional layer adjoining the first tunneling layer. The additional layer is selected from the group consisting of a retention layer and an additional composite layer. The additional composite layer comprises a second tunneling layer and a second storage layer adjoining the second tunneling layer. The semiconductor device further includes a blocking layer adjoining the first storage layer.
摘要翻译：半导体器件包括半导体衬底，半导体衬底上的顶栅极以及顶栅和半导体衬底之间的堆叠栅极。层叠栅极包括第一隧道层，邻接第一隧道层的第一存储层和邻接第一隧道层的附加层。附加层选自保留层和附加复合层。附加复合层包括邻接第二隧穿层的第二隧道层和第二存储层。半导体器件还包括邻接第一存储层的阻挡层。

8. 发明授权

US07579646B2 Flash memory with deep quantum well and high-K dielectric 有权
标题翻译：具有深量子阱和高K电介质的闪存
公开(公告)号：US07579646B2
公开(公告)日：2009-08-25
申请号：US11440667
申请日：2006-05-25
申请人： Ming-Tsong Wang , Tong-Chern Ong , Albert Chin , Chun-Hung Lai
发明人： Ming-Tsong Wang , Tong-Chern Ong , Albert Chin , Chun-Hung Lai
IPC分类号： H01L29/08
CPC分类号： H01L29/792 , H01L29/517 , H01L29/66833
摘要： A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably has a conduction band lower than a conduction band of silicon. The blocking layer is preferably formed of a high-k dielectric material.
摘要翻译：闪存单元包括形成在基板上的基板和栅极结构。栅极结构包括在衬底上的隧道层，隧道层上的存储层，存储层上的阻挡层和电介质上的栅电极。存储层优选具有比硅的导带低的导带。阻挡层优选由高k电介质材料形成。

9. 发明申请

US20080012138A1 One-time-programmable anti-fuse formed using damascene process 有权
标题翻译：使用镶嵌工艺形成一次性可编程反熔丝
公开(公告)号：US20080012138A1
公开(公告)日：2008-01-17
申请号：US11487849
申请日：2006-07-17
申请人： Ming-Tsong Wang , Tong-Chern Ong
发明人： Ming-Tsong Wang , Tong-Chern Ong
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power source. The stacked structure includes a bottom electrode, a top electrode, and an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer has a breakdown voltage lower than a pre-determined write voltage provided by the power source and higher than a pre-determined read voltage provided by the power source.
摘要翻译：半导体结构包括在半导体衬底上的半导体衬底，电源和层叠结构，并且耦合到电源。堆叠结构包括底部电极，顶部电极和顶部电极和底部电极之间的绝缘层，其中绝缘层具有低于由电源提供的预定写入电压的击穿电压，并且高于由电源提供的预定读取电压。

10. 发明申请

US20080067577A1 Multi-trapping layer flash memory cell 有权
标题翻译：多陷阱层闪存单元
公开(公告)号：US20080067577A1
公开(公告)日：2008-03-20
申请号：US11521805
申请日：2006-09-15
申请人： Ming-Tsong Wang , Tong-Chern Ong
发明人： Ming-Tsong Wang , Tong-Chern Ong
IPC分类号： H01L29/788
CPC分类号： H01L29/42348 , G11C11/5671 , G11C16/0466 , G11C16/10 , H01L21/28273 , H01L21/28282 , H01L29/7887 , H01L29/7923
摘要： A semiconductor device includes a semiconductor substrate, a top gate over the semiconductor substrate, and a stacked gate between the top gate and the semiconductor substrate. The stacked gate includes a first tunneling layer, a first storage layer adjoining the first tunneling layer, and an additional layer adjoining the first tunneling layer. The additional layer is selected from the group consisting of a retention layer and an additional composite layer. The additional composite layer comprises a second tunneling layer and a second storage layer adjoining the second tunneling layer. The semiconductor device further includes a blocking layer adjoining the first storage layer.
摘要翻译：半导体器件包括半导体衬底，半导体衬底上的顶栅极以及顶栅和半导体衬底之间的堆叠栅极。层叠栅极包括第一隧道层，邻接第一隧道层的第一存储层和邻接第一隧道层的附加层。附加层选自保留层和附加复合层。附加复合层包括邻接第二隧穿层的第二隧道层和第二存储层。半导体器件还包括邻接第一存储层的阻挡层。

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