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1. 发明授权

US08394721B2 Method for obtaining a layout design for an existing integrated circuit 有权
标题翻译：获得现有集成电路布局设计的方法
公开(公告)号：US08394721B2
公开(公告)日：2013-03-12
申请号：US13104986
申请日：2011-05-11
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/311
CPC分类号： H01L27/0203 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.
摘要翻译：一种用于获得现有集成电路的布局设计的方法，其中集成电路管芯以倾斜角抛光以形成倾斜的抛光表面，并且获得倾斜抛光表面的一个或多个图像。图像可以直接重叠，或者图像或图像可以用于提供信息以获得包括布局结构的至少一个重复单元结构的布局设计。

2. 发明申请

US20120287500A1 OPTICAL LENS AND OPTICAL MICROSCOPE SYSTEM USING THE SAME 审中-公开
标题翻译：光学透镜和光学显微镜系统
公开(公告)号：US20120287500A1
公开(公告)日：2012-11-15
申请号：US13106864
申请日：2011-05-13
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G02B21/02 , G02B3/02
CPC分类号： G02B5/005 , G02B21/02
摘要： An optical lens is provided in the present invention. The optical lens includes a first curved surface and an annular mask component on and in direct contact with the first curved surface, wherein the annular mask component shields a peripheral annular region of the optical lens from entry of light. The present invention further provides an optical microscope system using the same.
摘要翻译：在本发明中提供了一种光学透镜。光学透镜包括在第一弯曲表面上且与第一弯曲表面直接接触的第一弯曲表面和环形掩模部件，其中环形掩模部件屏蔽光学透镜的外围环形区域以防止光入射。本发明还提供一种使用其的光学显微镜系统。

3. 发明申请

US20120288968A1 Method for repairing a semiconductor structure having a current-leakage issue 审中-公开
标题翻译：修复具有电流泄漏问题的半导体结构的方法
公开(公告)号：US20120288968A1
公开(公告)日：2012-11-15
申请号：US13106837
申请日：2011-05-12
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A method for repairing a semiconductor structure having a current-leakage issue includes finding a semiconductor structure having a current-leakage issue through application of a test voltage from an electric test device and applying an electric power stress to the semiconductor structure to melt a stringer or a bridge between two conductive elements or to allow the stringer or the bridge to be oxidized.
摘要翻译：一种用于修复具有电流泄漏问题的半导体结构的方法包括通过施加来自电测试装置的测试电压来发现具有电流泄漏问题的半导体结构，并向半导体结构施加电力应力以熔化桁条或两个导电元件之间的桥梁或允许桁条或桥被氧化。

4. 发明申请

US20120288967A1 METHOD FOR PROCESSING CIRCUIT IN PACKAGE 审中-公开
标题翻译：用于处理包装中的电路的方法
公开(公告)号：US20120288967A1
公开(公告)日：2012-11-15
申请号：US13105909
申请日：2011-05-12
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/30 , H01L21/306
CPC分类号： H01L21/56 , H01L24/48 , H01L24/49 , H01L2224/48227 , H01L2224/49175 , H01L2924/00014 , H01L2924/12044 , H01L2924/14 , H01L2924/1434 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for decapsulating an integrated circuit package without the need of using a mask during the decapsulation process is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided. The caustic solution is capable of etching the molding compound and intermittently contacts a pre-selected area of the molding compound to etch the molding compound. As a consequence, the caustic solution removes the molding compound in the pre-selected area so the circuit element in the package is substantially exposed.
摘要翻译：公开了一种在解封装过程中不需要使用掩模的集成电路封装的封装方法。首先，提供一个包装。封装件至少包括电路元件和封装电路的模塑料。其次，同时提供苛性碱溶液。苛性溶液能够蚀刻模塑料并间歇地接触模塑料的预先选择的区域以蚀刻模塑料。因此，苛性溶液去除了预选区域中的模塑料，使得包装中的电路元件基本上暴露出来。

5. 发明申请

US20120288684A1 BUMP STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译： BUMP结构及其制造方法
公开(公告)号：US20120288684A1
公开(公告)日：2012-11-15
申请号：US13106841
申请日：2011-05-12
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B32B3/00 , B23K1/20 , B23K31/02
CPC分类号： H01L24/85 , H01L23/3121 , H01L23/4952 , H01L23/49575 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L25/0657 , H01L2224/1134 , H01L2224/13019 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48245 , H01L2224/48247 , H01L2224/48465 , H01L2224/4847 , H01L2224/48479 , H01L2224/48499 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/78301 , H01L2224/81191 , H01L2224/85 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , Y10T428/24612 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/4554
摘要： A bump structure including a base portion, an inlaid wire segment, and a protruding tail segment is provided. The base portion is bonded on a bonding site. The inlaid wire segment is pressed into a top surface of the base portion. The protruding tail segment extends from the inlaid wire segment. The methods for forming the bump structure are also provided.
摘要翻译：提供了包括基部，镶嵌线段和突出尾段的凸块结构。基部结合在接合部位上。嵌入的线段被压入基部的顶表面。突出的尾部段从嵌入的线段延伸。还提供了用于形成凸块结构的方法。

6. 发明申请

US20120289048A1 Method for obtaining a layout design for an existing integrated circuit 有权
标题翻译：获得现有集成电路布局设计的方法
公开(公告)号：US20120289048A1
公开(公告)日：2012-11-15
申请号：US13104986
申请日：2011-05-11
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/306 , H01L21/304
CPC分类号： H01L27/0203 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.
摘要翻译：一种用于获得现有集成电路的布局设计的方法，其中集成电路管芯以倾斜角抛光以形成倾斜的抛光表面，并且获得倾斜抛光表面的一个或多个图像。图像可以直接重叠，或者图像或图像可以用于提供信息以获得包括布局结构的至少一个重复单元结构的布局设计。

7. 发明申请

US20120288966A1 METHOD FOR DECAPSULATING INTEGRATED CIRCUIT PACKAGE 审中-公开
标题翻译：用于消除集成电路封装的方法
公开(公告)号：US20120288966A1
公开(公告)日：2012-11-15
申请号：US13105905
申请日：2011-05-12
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/30 , H01L21/306
CPC分类号： H01L21/31133 , H01L2224/48091 , H01L2924/12044 , H01L2924/00014 , H01L2924/00
摘要： A method for decapsulating an integrated circuit package in the absence of a mask is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided and drained. The caustic solution is capable of etching the molding compound while in continuous contact with the molding compound to etch the molding compound. As a consequence, the molding compound is removed so that the circuit element in the package is substantially exposed.
摘要翻译：公开了一种在没有掩模的情况下对集成电路封装进行封装的方法。首先，提供一个包装。封装件至少包括电路元件和封装电路的模塑料。第二，同时提供和排出苛性碱溶液。苛性溶液能够在与模塑料连续接触的同时刻蚀模塑料以蚀刻模塑料。结果，除去模塑料，使包装中的电路元件基本上露出。

8. 发明申请

US20120288355A1 Method for storing wafers 审中-公开
标题翻译：存储晶圆的方法
公开(公告)号：US20120288355A1
公开(公告)日：2012-11-15
申请号：US13105881
申请日：2011-05-11
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/677 , B65B31/00
CPC分类号： H01L21/67393
摘要： A method for storing wafers is disclosed. A plurality of wafers are placed into the wafer cassette box. The wafer cassette box is hermetically sealed and pumped down to vacuum for the wafer storage. Alternatively, the wafers carried by a holder conveyed on a wafer conveyor are placed into a pump-down chamber enclosing a section of the wafer conveyor. The pump-down chamber is hermetic sealed and pumped down to vacuum for the wafer storage on the wafer conveyor.
摘要翻译：公开了一种用于存储晶片的方法。多个晶片被放置在晶片盒盒中。将晶片盒盒密封并泵送到真空以进行晶片储存。或者，由在晶片传送器上输送的保持器承载的晶片被放置在包围晶片传送器的一部分的抽空室中。抽气室被气密密封并泵送到真空以用于在晶片输送机上的晶片储存。

9. 发明授权

US08912595B2 Trench MOS structure and method for forming the same 有权
标题翻译：沟槽MOS结构及其形成方法
公开(公告)号：US08912595B2
公开(公告)日：2014-12-16
申请号：US13106852
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66 , H01L21/308
CPC分类号： H01L29/7813 , H01L21/3083 , H01L29/4236 , H01L29/66666 , H01L29/66734 , H01L29/7827
摘要： A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.
摘要翻译：公开了一种沟槽MOS结构。沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。掺杂阱具有第二导电类型并且设置在外延层上。掺杂区域具有第一导电类型并且被布置在掺杂阱上。沟槽栅极部分地设置在掺杂区域中。沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

10. 发明授权

US08816715B2 MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test 有权
标题翻译： MOS测试结构，用于形成MOS测试结构的方法和用于进行晶片验收测试的方法
公开(公告)号：US08816715B2
公开(公告)日：2014-08-26
申请号：US13105913
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G01R31/02 , G01R31/26 , H01L21/66 , G01R31/28
CPC分类号： H01L22/34 , G01R31/02 , G01R31/26 , G01R31/2644 , G01R31/2831
摘要： A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.
摘要翻译：公开了MOS测试结构。划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接到外延层，使得测试通孔能够一起测试外延层和衬底。

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