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1. 发明申请

US20120286836A1 Built-in Self-test Circuit for Voltage Controlled Oscillators 有权
标题翻译：用于压控振荡器的内置自检电路
公开(公告)号：US20120286836A1
公开(公告)日：2012-11-15
申请号：US13103571
申请日：2011-05-09
申请人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03K3/84
CPC分类号： G01R31/2824
摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.
摘要翻译：用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

2. 发明申请

US20120286888A1 Switched Capacitor Array for Voltage Controlled Oscillator 审中-公开
标题翻译：用于压控振荡器的开关电容阵列
公开(公告)号：US20120286888A1
公开(公告)日：2012-11-15
申请号：US13103592
申请日：2011-05-09
申请人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03B5/12 , H03H11/00
CPC分类号： H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2201/0266
摘要： A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code.
摘要翻译：一种系统包括压控振荡器，其包括电感器和可变电容器以及与可变电容器并联连接的开关电容器阵列。开关电容器阵列还包括多个电容器组，其中使用温度计代码来控制每个电容器组。此外，当开关电容器阵列由n位温度计代码控制时，开关电容器阵列为压控振荡器的振荡频率提供N个调谐步骤。

3. 发明授权

US09397729B2 Through chip coupling for signal transport 有权
标题翻译：通过芯片耦合进行信号传输
公开(公告)号：US09397729B2
公开(公告)日：2016-07-19
申请号：US12946072
申请日：2010-11-15
申请人： Tzu-Jin Yeh , Hsieh-Hung Hsieh , Jun-De Jin , Ming Hsien Tsai , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Tzu-Jin Yeh , Hsieh-Hung Hsieh , Jun-De Jin , Ming Hsien Tsai , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H04B5/00
CPC分类号： H04B5/0081
摘要： Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.
摘要翻译：芯片耦合用于信号传输，其中在第一集成电路（IC）芯片上的第一线圈和第二IC芯片上的第二线圈之间形成接口。第一线圈耦合到天线。第二线圈耦合到放大器电路。第二线圈不与第一线圈直接接触。第一线圈和第二线圈在天线和第一放大器电路之间通信地传送信号。

4. 发明授权

US08729968B2 Built-in self-test circuit for voltage controlled oscillators 有权
标题翻译：用于压控振荡器的内置自检电路
公开(公告)号：US08729968B2
公开(公告)日：2014-05-20
申请号：US13103571
申请日：2011-05-09
申请人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03L5/00
CPC分类号： G01R31/2824
摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.
摘要翻译：用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

5. 发明授权

US08334571B2 Junction varactor for ESD protection of RF circuits 有权
标题翻译：用于射频电路ESD保护的结型变容二极管
公开(公告)号：US08334571B2
公开(公告)日：2012-12-18
申请号：US12731562
申请日：2010-03-25
申请人： Ming-Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Ming-Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H01L23/60 , H01L23/64 , H01L29/08
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.
摘要翻译： ESD保护装置包括设置在形成第一二极管的第二半导体类型的衬底中的第一半导体类型的第一阱。第二半导体类型的第二阱形成在衬底中以与第一阱形成第二二极管。第一半导体类型的第一多个掺杂区域形成在第一阱的上表面中。第二半导体类型的第二多个掺杂区域形成在第一阱的上表面中，其与第一阱形成第三二极管。多个STI区域形成在第一阱的上表面中。每个STI区域设置在第一和第二半导体类型的掺杂区域之间。当在第一或第二多个掺杂区域中的一个处接收ESD电压尖峰时，第三二极管提供电流旁路。

6. 发明申请

US20110260819A1 CONTINUOUSLY TUNABLE INDUCTOR WITH VARIABLE RESISTORS 审中-公开
标题翻译：具有可变电阻器的连续电容器
公开(公告)号：US20110260819A1
公开(公告)日：2011-10-27
申请号：US12766970
申请日：2010-04-26
申请人： Tzu-Jin Yeh , Kal-Wen Tan , Ming Hsien Tsai , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Tzu-Jin Yeh , Kal-Wen Tan , Ming Hsien Tsai , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H01F21/00
CPC分类号： H01F21/02 , H01F21/005 , H01F2021/125
摘要： An integrated tunable inductor includes a primary inductor having a plurality of inductor turns, at least one closed loop eddy current coil proximate the primary inductor, and at least one variable resistor integrated in series with the eddy current coil.
摘要翻译：集成可调电感器包括具有多个电感线圈的初级电感器，至少一个靠近初级电感器的闭环涡流线圈以及与涡流线圈串联集成的至少一个可变电阻器。

7. 发明授权

US09129940B2 RF calibration through-chip inductive coupling 有权
标题翻译： RF校准片上感应耦合
公开(公告)号：US09129940B2
公开(公告)日：2015-09-08
申请号：US13419911
申请日：2012-03-14
申请人： Hsieh-Hung Hsieh , Yi-Hsuan Liu , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Hsieh-Hung Hsieh , Yi-Hsuan Liu , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： G01R35/00 , H01L23/48 , H01L23/66 , H01L25/065 , H04B5/00
CPC分类号： H01L23/48 , H01L23/66 , H01L25/0657 , H01L2225/06531 , H01L2924/0002 , H04B5/0075 , H01L2924/00
摘要： An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.
摘要翻译：集成电路包括在垂直堆叠中耦合到第一芯片的第一芯片和第二芯片。第一芯片包括射频电路和电耦合到射频电路的第一线圈。第二芯片包括校准电路和电耦合到校准电路的第二线圈。校准电路被配置为通过第一和第二线圈之间的感应耦合来校准设置在第一芯片上的射频电路。

8. 发明申请

US20110265051A1 Method for Substrate Noise Analysis 有权
标题翻译：基板噪声分析方法
公开(公告)号：US20110265051A1
公开(公告)日：2011-10-27
申请号：US12766732
申请日：2010-04-23
申请人： Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
发明人： Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.
摘要翻译：根据实施例，用于衬底噪声分析的方法包括使用基于第一处理器的系统，创建和模拟包括晶体管的多端子模型的电路原理图，然后基于电路原理图中所示的特性创建布局和仿真结果的模拟。多端子模型包括源极端子，栅极端子，漏极端子，主体端子和保护环端子。

9. 发明授权

US08627253B2 Method for substrate noise analysis 有权
标题翻译：衬底噪声分析方法
公开(公告)号：US08627253B2
公开(公告)日：2014-01-07
申请号：US12766732
申请日：2010-04-23
申请人： Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
发明人： Tzu-Jin Yeh , Kal-Wen Tan , Chewn-Pu Jou , Sally Liu , Fu-Lung Hsueh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.
摘要翻译：根据实施例，用于衬底噪声分析的方法包括使用基于第一处理器的系统，创建和模拟包括晶体管的多端子模型的电路原理图，然后基于电路原理图中所示的特性创建布局和仿真结果的模拟。多端子模型包括源极端子，栅极端子，漏极端子，主体端子和保护环端子。

10. 发明授权

US08451033B2 Millimeter-wave wideband frequency doubler 有权
标题翻译：毫米波宽带倍频器
公开(公告)号：US08451033B2
公开(公告)日：2013-05-28
申请号：US12967160
申请日：2010-12-14
申请人： Po-Yi Wu , Hsieh-Hung Hsieh , Ho-Hsiang Chen , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Po-Yi Wu , Hsieh-Hung Hsieh , Ho-Hsiang Chen , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03B19/00
CPC分类号： H03B19/00
摘要： A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.
摘要翻译：用于分布式倍频器的毫米波宽带倍频器级包括：差分输入对晶体管，每个晶体管具有相应的栅极，漏极和源极端子，其中源极端子耦合到第一电源节点，并且漏极端子在第一节点耦合到第二电源节点; 耦合到晶体管的栅极端子的第一和第二对带通栅极线; 以及耦合到晶体管的漏极端子的一对带通漏极线。

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