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1. 发明授权

US08241823B2 Method of fabrication of a semiconductor device having reduced pitch 有权
标题翻译：具有减小的间距的半导体器件的制造方法
公开(公告)号：US08241823B2
公开(公告)日：2012-08-14
申请号：US13248932
申请日：2011-09-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03G5/00 , H01L21/302 , H01L21/461
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为虚线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

2. 发明授权

US08039179B2 Integrated circuit layout design 有权
标题翻译：集成电路布局设计
公开(公告)号：US08039179B2
公开(公告)日：2011-10-18
申请号：US12980764
申请日：2010-12-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03C5/00 , G03F9/00
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为假线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

3. 发明授权

US07862962B2 Integrated circuit layout design 有权
标题翻译：集成电路布局设计
公开(公告)号：US07862962B2
公开(公告)日：2011-01-04
申请号：US12356405
申请日：2009-01-20
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.
摘要翻译：提供了一种包括集成电路的布局设计的方法。提供了第一种模式。第一图案包括虚线特征的阵列和与虚线特征相邻的多个间隔元件。提供了第二种模式。第二图案定义了集成电路器件的有源区。确定有源区的边缘间隔元件。假线特征阵列的虚线特征被偏置（例如，宽度增加），虚线特征与边缘间隔元件相邻。

4. 发明申请

US20110151359A1 INTEGRATED CIRCUIT LAYOUT DESIGN 有权
标题翻译：集成电路布局设计
公开(公告)号：US20110151359A1
公开(公告)日：2011-06-23
申请号：US12980764
申请日：2010-12-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03F1/00 , G03F7/20 , G06F17/50
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为假线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

5. 发明申请

US20120021589A1 METHOD OF FABRICATION OF A SEMICONDUCTOR DEVICE HAVING REDUCED PITCH 有权
标题翻译：具有减少电极的半导体器件的制造方法
公开(公告)号：US20120021589A1
公开(公告)日：2012-01-26
申请号：US13248932
申请日：2011-09-29
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： H01L21/311 , H01L21/30
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
摘要翻译：提供了一种包括光掩模的光刻设备。光掩模包括具有多个特征的图案，在示例中为虚线特征。该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。该装置可以包括可以限定有源区域的第二光掩模。具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

6. 发明申请

US20100183961A1 INTEGRATED CIRCUIT LAYOUT DESIGN 有权
标题翻译：集成电路布局设计
公开(公告)号：US20100183961A1
公开(公告)日：2010-07-22
申请号：US12356405
申请日：2009-01-20
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03F7/20 , G06F17/50 , G03F1/00 , G03F7/40
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.
摘要翻译：提供了一种包括集成电路的布局设计的方法。提供了第一种模式。第一图案包括虚线特征的阵列和与虚线特征相邻的多个间隔元件。提供了第二种模式。第二图案定义了集成电路器件的有源区。确定有源区的边缘间隔元件。假线特征阵列的虚线特征被偏置（例如，宽度增加），虚线特征与边缘间隔元件相邻。

7. 发明申请

US20100203734A1 METHOD OF PITCH HALVING 有权
标题翻译：倾斜方法
公开(公告)号：US20100203734A1
公开(公告)日：2010-08-12
申请号：US12370152
申请日：2009-02-12
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Ming-Ching Chang , Jeff J. Xu
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Ming-Ching Chang , Jeff J. Xu
IPC分类号： H01L21/467
CPC分类号： H01L21/3086 , H01L21/3088 , H01L21/823828 , H01L21/823871 , Y10S438/947
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.
摘要翻译：本公开提供了一种制造半导体器件的方法，该半导体器件包括在衬底上形成掩模层，在掩模层上形成具有第一虚拟特征和第二虚拟特征的虚设层，形成第一和第二间隔物顶部以覆盖顶部分别形成第一和第二间隔套筒以分别围绕第一和第二虚拟特征的侧面部分，去除第一间隔物顶部和第一虚拟特征，同时保护第二虚拟特征，去除第一间隔套筒的第一端部和第二端部，以形成间隔件翅片，并且使用间隔件翅片作为第一掩模元件并将第二虚拟特征图案化为掩模层作为第二掩模元件。

8. 发明授权

US07989355B2 Method of pitch halving 有权
标题翻译：节距减法的方法
公开(公告)号：US07989355B2
公开(公告)日：2011-08-02
申请号：US12370152
申请日：2009-02-12
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Ming-Ching Chang , Jeff J. Xu
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Ming-Ching Chang , Jeff J. Xu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3086 , H01L21/3088 , H01L21/823828 , H01L21/823871 , Y10S438/947
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.
摘要翻译：本公开提供了一种制造半导体器件的方法，该半导体器件包括在衬底上形成掩模层，在掩模层上形成具有第一虚拟特征和第二虚拟特征的虚设层，形成第一和第二间隔物顶部以覆盖顶部分别形成第一和第二间隔套筒以分别围绕第一和第二虚拟特征的侧面部分，去除第一间隔物顶部和第一虚拟特征，同时保护第二虚拟特征，去除第一间隔套筒的第一端部和第二端部，以形成间隔件翅片，并且使用间隔件翅片作为第一掩模元件并将第二虚拟特征图案化为掩模层作为第二掩模元件。

9. 发明授权

US08268683B2 Method for reducing interfacial layer thickness for high-K and metal gate stack 有权
标题翻译：降低高K和金属栅极叠层的界面层厚度的方法
公开(公告)号：US08268683B2
公开(公告)日：2012-09-18
申请号：US12782859
申请日：2010-05-19
申请人： Liang-Gi Yao , Chun-Hu Cheng , Chen-Yi Lee , Jeff J. Xu , Clement Hsingjen Wann
发明人： Liang-Gi Yao , Chun-Hu Cheng , Chen-Yi Lee , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： H01L21/8249
CPC分类号： H01L29/513 , H01L21/02172 , H01L21/022 , H01L21/28158 , H01L21/28211 , H01L21/283 , H01L29/42364 , H01L29/517 , H01L29/78
摘要： A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.
摘要翻译：提供了一种用于降低高k电介质和金属栅极叠层的界面层（IL）厚度的方法。在一个实施例中，该方法包括在半导体衬底上形成界面层，蚀刻回界面层，在界面层上沉积高k电介质材料，以及在高k电介质材料上形成金属栅极。 IL可以是化学氧化物，臭氧化氧化物，热氧化物，或者由化学氧化物等的紫外线臭氧（UVO）氧化过程形成.II的回蚀可以通过稀释HF（DHF）工艺，蒸气HF工艺，或任何其他合适的过程。该方法还可以包括在沉积高k介电材料之前在界面层上进行UV固化或低热预算退火。

10. 发明授权

US08470659B2 Method for reducing interfacial layer thickness for high-k and metal gate stack 有权
标题翻译：降低高k和金属栅极叠层的界面层厚度的方法
公开(公告)号：US08470659B2
公开(公告)日：2013-06-25
申请号：US13595599
申请日：2012-08-27
申请人： Liang-Gi Yao , Chun-Hu Cheng , Chen-Yi Lee , Jeff J. Xu , Clement Hsingjen Wann
发明人： Liang-Gi Yao , Chun-Hu Cheng , Chen-Yi Lee , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： H01L21/8249
CPC分类号： H01L29/513 , H01L21/02172 , H01L21/022 , H01L21/28158 , H01L21/28211 , H01L21/283 , H01L29/42364 , H01L29/517 , H01L29/78
摘要： This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.
摘要翻译：该描述涉及包括在半导体衬底上形成界面层的方法。该方法还包括蚀刻回界面层。该方法还包括在界面层上进行紫外线（UV）固化过程。 UV固化方法包括将每分钟10标准立方厘米（sccm）的气体流速提供到5标准升/分钟（slm），其中气体包括惰性气体，并且在小于或等于的温度下加热界面层至700℃。该方法还包括在界面层上沉积高k介电材料。

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