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1. 发明授权

US08429332B2 Multi-channel hybrid density memory storage device and control method thereof 有权
公开(公告)号：US08429332B2
公开(公告)日：2013-04-23
申请号：US12382442
申请日：2009-03-17
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
IPC分类号： G06F13/00 , G06F13/28 , G06F11/00 , H03M13/00
CPC分类号： G06F12/0246 , G06F11/1048 , G06F2212/7208
摘要： The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data.

2. 发明申请

US20090307418A1 Multi-channel hybrid density memory storage device and control method thereof 有权
标题翻译：多通道混合密度存储器及其控制方法
公开(公告)号：US20090307418A1
公开(公告)日：2009-12-10
申请号：US12382442
申请日：2009-03-17
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
IPC分类号： G06F12/06 , H03M13/09
CPC分类号： G06F12/0246 , G06F11/1048 , G06F2212/7208
摘要： The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data.
摘要翻译：本发明公开了一种用于访问用户数据的多通道混合密度存储装置的控制方法。存储装置包括多个低密度存储器（LDM）和高密度存储器（HDM）。该方法的步骤包括：首先确定用户数据发送的位置; 然后，使用具有不同纠错能力的两个纠错电路中的一个对用户数据进行编码或解码。

3. 发明申请

US20100082883A1 Hybrid density memory system and control method thereof 审中-公开
标题翻译：混合密度记忆系统及其控制方法
公开(公告)号：US20100082883A1
公开(公告)日：2010-04-01
申请号：US12379698
申请日：2009-02-26
申请人： Ming-Dar Chen , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7202 , G11C2211/5641
摘要： A control method of a memory system for accessing an updated data between a host and the memory system is provided. The host has storage space which is divided into a plurality of logical segments to access the data. The system includes a high density memory and a low density memory, and the high density memory includes a plurality of physical segments to access the data. The control method includes the following steps: first, providing a LDM table in the memory system to indicate the allocation information of the low density memory; finally, deciding where the data is written to is according to its properties and the LDM table.
摘要翻译：提供了一种用于访问主机和存储器系统之间的更新数据的存储器系统的控制方法。主机具有被分成多个逻辑段以存取数据的存储空间。该系统包括高密度存储器和低密度存储器，并且高密度存储器包括用于访问数据的多个物理段。该控制方法包括以下步骤：首先，在存储器系统中提供LDM表以指示低密度存储器的分配信息; 最后，根据其属性和LDM表来决定数据写入的位置。

4. 发明申请

US20100332738A1 STORAGE DEVICE AND DATA PROCESSING METHOD 审中-公开
标题翻译：存储设备和数据处理方法
公开(公告)号：US20100332738A1
公开(公告)日：2010-12-30
申请号：US12785405
申请日：2010-05-21
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Tzu-Wei Fang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Tzu-Wei Fang , Hsiang-An Hsieh
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C16/349 , G11C16/04 , G11C29/08 , G11C2029/0401 , G11C2029/0409
摘要： A storage device for connecting to a host system includes a flash memory and a controller coupled to the flash memory. The flash memory includes a plurality of memory blocks. The controller writes test data to the flash memory, and compares the test data read from the flash memory with the original test data to generate a bit error message corresponding to the flash memory. Then, the controller chooses and labels a quick read block from the plurality of memory blocks according to the bit error message, and finally writes a specific file to the quick read block.
摘要翻译：用于连接到主机系统的存储设备包括闪存和耦合到闪速存储器的控制器。闪存包括多个存储块。控制器将测试数据写入闪速存储器，并将从闪存读取的测试数据与原始测试数据进行比较，以产生与闪存相对应的位错误消息。然后，控制器根据位错误消息从多个存储块中选择并标记快速读块，最后将特定文件写入快速读块。

5. 发明授权

US08307163B2 Hybrid density memory storage device 有权
标题翻译：混合密度存储器
公开(公告)号：US08307163B2
公开(公告)日：2012-11-06
申请号：US12050593
申请日：2008-03-18
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Hui-Neng Chang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Hui-Neng Chang , Hsiang-An Hsieh
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7208 , G06F2212/7211 , G11C11/56 , G11C2211/5641
摘要： The present invention discloses a hybrid density memory storage device configured to store data responsive to a host and a file system thereof. The hybrid density memory storage device includes a non-volatile memory, a hot data buffer and a control unit. The non-volatile memory includes a high density storage space and a low density storage space. The control unit is coupled between the host, the non-volatile memory, and the hot data buffer. The control unit has a hot list used for recording a plurality of logical locations of hot data, and the control unit is capable of accessing data in/out the hot data buffer in accordance with the hot list.
摘要翻译：本发明公开了一种混合密度存储器存储装置，被配置为存储响应于主机及其文件系统的数据。混合密度存储器存储装置包括非易失性存储器，热数据缓冲器和控制单元。非易失性存储器包括高密度存储空间和低密度存储空间。控制单元耦合在主机，非易失性存储器和热数据缓冲器之间。控制单元具有用于记录热数据的多个逻辑位置的热列表，并且控制单元能够根据热列表访问/输出热数据缓冲器中的数据。

6. 发明授权

US08205036B2 Non-volatile memory and controlling method thereof 有权
标题翻译：非易失性存储器及其控制方法
公开(公告)号：US08205036B2
公开(公告)日：2012-06-19
申请号：US12509287
申请日：2009-07-24
申请人： Ming-Dar Chen , Hsiang-An Hsieh , Chuan-Sheng Lin
发明人： Ming-Dar Chen , Hsiang-An Hsieh , Chuan-Sheng Lin
IPC分类号： G06F12/00
CPC分类号： G11C16/349 , G06F12/0246 , G06F2212/7211 , G11C16/3495
摘要： A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks. If the standard deviation of the erase counts is bigger than the predetermined threshold point, starts for a second amount of cycles and moves the static data stored a second number of memory blocks.
摘要翻译：本发明的非易失性存储器包括多个存储块和静态损耗均衡装置。静态损耗均衡装置包括用于存储存储块的擦除计数的存储单元和用于从存储单元获取擦除计数的控制单元，并且基于EC计算标准偏差，并且确定静态磨损的方式调平周期根据标准偏差。决定静态磨损均衡循环的方式的控制单元包括设置至少一个预定阈值点并判断擦除计数的标准偏差是否小于预定阈值点的步骤。如果擦除计数的标准偏差小于预定阈值点，则静态磨损均衡循环开始第一次循环，并且移动存储有第一数量的存储块的静态数据。如果擦除计数的标准偏差大于预定的阈值点，则开始第二个循环量并且移动存储有第二数量的存储器块的静态数据。

7. 发明申请

US20090300273A1 Flash memory apparatus with automatic interface mode switching 有权
标题翻译：具有自动接口模式切换的闪存设备
公开(公告)号：US20090300273A1
公开(公告)日：2009-12-03
申请号：US12232771
申请日：2008-09-24
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Hsiang-An Hsieh
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F13/1694
摘要： A flash memory controller with automatic interface mode switching is applied to a flash memory apparatus with a plurality of flash memories and the controller contains: a memory interface, a microprocessor, and an interface mode controller. The microprocessor recognizes the supported interface mode of every flash memory connected with the memory interface in an initial setting process, and individually sets the corresponding interface mode setting value into the interface mode controller. Thus, when the flash memory apparatus is operating in a normal operation state, the interface mode controller can output the corresponding interface mode setting value according to the present enabled flash memory, and the memory interface can adjust and switch the interface mode according to the interface mode setting value outputted by the interface mode controller. Thereby, the present invention can achieve the purpose whereby the flash memory apparatus can speed up accessing and increase efficiency.
摘要翻译：具有自动接口模式切换的闪速存储器控制器被应用于具有多个闪速存储器的闪存装置，并且控制器包括：存储器接口，微处理器和接口模式控制器。微处理器在初始设置过程中识别与存储器接口连接的每个闪存的支持的接口模式，并将相应的接口模式设置值单独设置为接口模式控制器。因此，当闪存装置工作在正常工作状态时，接口模式控制器可根据当前使能的闪存输出相应的接口模式设置值，并且存储器接口可以根据接口调整和切换接口模式模式设定值由界面模式控制器输出。因此，本发明可以实现闪速存储装置可以加速访问并提高效率的目的。

8. 发明授权

US08185686B2 Memory system and a control method thereof 有权
标题翻译：存储器系统及其控制方法
公开(公告)号：US08185686B2
公开(公告)日：2012-05-22
申请号：US12385228
申请日：2009-04-02
申请人： Ming-Dar Chen , Hsiang-An Hsieh , Chuan-Sheng Lin
发明人： Ming-Dar Chen , Hsiang-An Hsieh , Chuan-Sheng Lin
IPC分类号： G06F13/10
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7211
摘要： A control method for the memory system is suitable for a memory system to process the user data from a host. The control unit divides the address of the storage space of the host into a plurality of logical segments for accessing data. The memory system provides a storage space with a plurality of physical segments to access data. The control method comprises the following steps. Firstly, a master table is provided in the physical memory for recording the mapping relation between the addresses of the logical units and the addresses of the physical units. When the data is written, the mapping relation between the addresses of the logical units and the addresses of the physical units is adjusted according to the wear of the physical units. Finally, the data is written into the physical segment according to the master table.
摘要翻译：用于存储器系统的控制方法适用于从主机处理用户数据的存储器系统。控制单元将主机的存储空间的地址划分为用于访问数据的多个逻辑段。存储器系统提供具有多个物理段的存储空间以访问数据。控制方法包括以下步骤。首先，在物理存储器中设置主表以记录逻辑单元的地址和物理单元的地址之间的映射关系。当写入数据时，根据物理单元的磨损来调整逻辑单元的地址和物理单元的地址之间的映射关系。最后，根据主表将数据写入物理段。

9. 发明授权

US07921339B2 Flash storage device with data correction function 有权
标题翻译：具有数据修正功能的闪存设备
公开(公告)号：US07921339B2
公开(公告)日：2011-04-05
申请号：US12232124
申请日：2008-09-11
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Hsiang-An Hsieh
IPC分类号： G06F11/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A flash controller performs a data correction function while executing a copy back procedure for a flash memory, and the flash memory includes at least one memory unit and a page buffer. The flash controller contains: a transmission buffer, an error correction unit, a correction information register, and a microprocessor. The microprocessor reads out a data from, the page buffer and stores the data into the transmission buffer after producing a read instruction of page copy to the flash memory. The microprocessor controls the error correction unit to check and correct the data in the transmission buffer and calculate a check result. The microprocessor produces a different program command to record the corrected data into the memory unit according to the data error quantity of the check result. Thereby, the present invention can achieve the purpose of improving the flash controller in reliability and access efficiency.
摘要翻译：闪存控制器在执行闪速存储器的复制过程时执行数据校正功能，并且闪速存储器包括至少一个存储器单元和页面缓冲器。闪存控制器包括：发送缓冲器，纠错单元，校正信息寄存器和微处理器。微处理器从页缓冲器中读出数据，并且在产生对闪存的页复制的读指令之后将数据存储到发送缓冲器中。微处理器控制纠错单元，检查和纠正发送缓冲器中的数据，并计算检查结果。微处理器产生不同的程序命令，以根据检查结果的数据错误量将校正的数据记录到存储器单元中。由此，本发明可以达到改善闪存控制器的可靠性和访问效率的目的。

10. 发明申请

US20090307537A1 Flash storage device with data correction function 有权
标题翻译：具有数据修正功能的闪存设备
公开(公告)号：US20090307537A1
公开(公告)日：2009-12-10
申请号：US12232124
申请日：2008-09-11
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Hsiang-An Hsieh
IPC分类号： G06F11/00 , G06F12/02 , G06F11/07
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A flash controller performs a data correction function while executing a copy back procedure for a flash memory, and the flash memory includes at least one memory unit and a page buffer. The flash controller contains: a transmission buffer, an error correction unit, a correction information register, and a microprocessor. The microprocessor reads out a data from, the page buffer and stores the data into the transmission buffer after producing a read instruction of page copy to the flash memory. The microprocessor controls the error correction unit to check and correct the data in the transmission buffer and calculate a check result. The microprocessor produces a different program command to record the corrected data into the memory unit according to the data error quantity of the check result. Thereby, the present invention can achieve the purpose of improving the flash controller in reliability and access efficiency.
摘要翻译：闪存控制器在执行闪速存储器的复制过程时执行数据校正功能，并且闪速存储器包括至少一个存储器单元和页面缓冲器。闪存控制器包括：发送缓冲器，纠错单元，校正信息寄存器和微处理器。微处理器从页缓冲器中读出数据，并且在产生对闪存的页复制的读指令之后将数据存储到发送缓冲器中。微处理器控制纠错单元，检查和纠正发送缓冲器中的数据，并计算检查结果。微处理器产生不同的程序命令，以根据检查结果的数据错误量将校正的数据记录到存储器单元中。由此，本发明可以达到改善闪存控制器的可靠性和访问效率的目的。

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