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1. 发明授权

US08008141B2 Method of fabricating a semiconductor device with multiple channels 有权
标题翻译：制造具有多个通道的半导体器件的方法
公开(公告)号：US08008141B2
公开(公告)日：2011-08-30
申请号：US12503594
申请日：2009-07-15
申请人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
发明人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
IPC分类号： H01L21/8232
CPC分类号： H01L29/78696 , H01L29/1083 , H01L29/66787
摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.
摘要翻译：具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并具有彼此相对的侧壁的一对导电区域。在导电区域之间的半导体衬底上设置有部分绝缘层。至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接到第一个方向。栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

2. 发明授权

US07579657B2 Semiconductor device with multiple channels 有权
标题翻译：具有多个通道的半导体器件
公开(公告)号：US07579657B2
公开(公告)日：2009-08-25
申请号：US11517211
申请日：2006-09-07
申请人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
发明人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/1083 , H01L29/66787
摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.
摘要翻译：具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并且具有彼此面对的侧壁的一对导电区域。在导电区域之间的半导体衬底上设置有部分绝缘层。至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接到第一个方向。栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

3. 发明申请

US20090275177A1 SEMICONDUCTOR DEVICE WITH MULTIPLE CHANNELS AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有多个通道的半导体器件及其制造方法
公开(公告)号：US20090275177A1
公开(公告)日：2009-11-05
申请号：US12503594
申请日：2009-07-15
申请人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
发明人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/1083 , H01L29/66787
摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.
摘要翻译：具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并且具有彼此面对的侧壁的一对导电区域。在导电区域之间的半导体衬底上设置有部分绝缘层。至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接到第一个方向。栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

4. 发明申请

US20070158679A1 Semiconductor device with multiple channels and method of fabricating the same 有权
标题翻译：具有多个通道的半导体器件及其制造方法
公开(公告)号：US20070158679A1
公开(公告)日：2007-07-12
申请号：US11517211
申请日：2006-09-07
申请人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
发明人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
IPC分类号： H01L29/74
CPC分类号： H01L29/78696 , H01L29/1083 , H01L29/66787
摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.
摘要翻译：具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并具有彼此相对的侧壁的一对导电区域。在导电区域之间的半导体衬底上设置有部分绝缘层。至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接到第一个方向。栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

5. 发明授权

US07955932B2 Single electron transistor and method of manufacturing the same 有权
标题翻译：单电子晶体管及其制造方法
公开(公告)号：US07955932B2
公开(公告)日：2011-06-07
申请号：US11905758
申请日：2007-10-03
申请人： Sung-Dae Suk , Kyoung-Hwan Yeo , Ming Li , Yun-Young Yeoh
发明人： Sung-Dae Suk , Kyoung-Hwan Yeo , Ming Li , Yun-Young Yeoh
IPC分类号： H01L21/336 , H01L31/00
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/66439 , Y10S438/962 , Y10S977/937 , Y10S977/938
摘要： A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.
摘要翻译：单电子晶体管包括分离在衬底上的源极/漏极层，连接源极/漏极层的至少一个纳米线沟道，纳米线沟道中的多个氧化物沟道区域，绝缘纳米线的至少一部分的氧化物沟道区域通道，在由多个氧化物通道区域绝缘的纳米线通道的部分中的量子点和围绕量子点的栅电极。

6. 发明授权

US08124961B2 Single electron transistor 有权
标题翻译：单电子晶体管
公开(公告)号：US08124961B2
公开(公告)日：2012-02-28
申请号：US13152900
申请日：2011-06-03
申请人： Sung-Dae Suk , Kyoung-Hwan Yeo , Ming Li , Yun-Young Yeoh
发明人： Sung-Dae Suk , Kyoung-Hwan Yeo , Ming Li , Yun-Young Yeoh
IPC分类号： H01L29/06 , H01L31/00 , H01L21/02
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/66439 , Y10S438/962 , Y10S977/937 , Y10S977/938
摘要： A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.
摘要翻译：单电子晶体管包括分离在衬底上的源极/漏极层，连接源极/漏极层的至少一个纳米线沟道，纳米线沟道中的多个氧化物沟道区域，绝缘纳米线的至少一部分的氧化物沟道区域通道，在由多个氧化物通道区域绝缘的纳米线通道的部分中的量子点和围绕量子点的栅电极。

7. 发明申请

US20080246021A1 Single electron transistor and method of manufacturing the same 有权
标题翻译：单电子晶体管及其制造方法
公开(公告)号：US20080246021A1
公开(公告)日：2008-10-09
申请号：US11905758
申请日：2007-10-03
申请人： Sung-Dae Suk , Kyoung-Hwan Yeo , Ming Li , Yun-Young Yeoh
发明人： Sung-Dae Suk , Kyoung-Hwan Yeo , Ming Li , Yun-Young Yeoh
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/66439 , Y10S438/962 , Y10S977/937 , Y10S977/938
摘要： A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.
摘要翻译：单电子晶体管包括分离在衬底上的源极/漏极层，连接源极/漏极层的至少一个纳米线沟道，纳米线沟道中的多个氧化物沟道区域，绝缘纳米线的至少一部分的氧化物沟道区域通道，在由多个氧化物通道区域绝缘的纳米线通道的部分中的量子点和围绕量子点的栅电极。

8. 发明授权

US08680588B2 Field effect transistor with buried gate pattern 有权
标题翻译：具有掩埋栅极图案的场效应晶体管
公开(公告)号：US08680588B2
公开(公告)日：2014-03-25
申请号：US12072440
申请日：2008-02-26
申请人： Ming Li , Dong-Uk Choi , Chang-Woo Oh , Dong-Won Kim , Min-Sang Kim , Sung-Hwan Kim , Kyoung-Hwan Yeo
发明人： Ming Li , Dong-Uk Choi , Chang-Woo Oh , Dong-Won Kim , Min-Sang Kim , Sung-Hwan Kim , Kyoung-Hwan Yeo
IPC分类号： H01L29/66
CPC分类号： H01L29/7883 , H01L27/108 , H01L27/10802 , H01L29/42336 , H01L29/42392 , H01L29/66825 , H01L29/7841
摘要： A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.
摘要翻译：场效应晶体管包括通过被隧道绝缘膜包围而电隔离的掩埋栅极图案。场效应晶体管还包括由源极和漏极区域浮置的沟道区，栅极绝缘膜和隧道绝缘膜。掩埋栅极图案和隧道绝缘膜延伸到源极和漏极区域。因此，场效应晶体管有效地将电荷载流子存储在掩埋栅极图案和浮动沟道区域中。

9. 发明申请

US20080142904A1 Field effect transistor with buried gate pattern 有权
公开(公告)号：US20080142904A1
公开(公告)日：2008-06-19
申请号：US12072440
申请日：2008-02-26
申请人： Ming Li , Dong-Uk Choi , Chang Woo Oh , Dong-Won Kim , Min-Sang Kim , Sung-Hwan Kim , Kyoung-Hwan Yeo
发明人： Ming Li , Dong-Uk Choi , Chang Woo Oh , Dong-Won Kim , Min-Sang Kim , Sung-Hwan Kim , Kyoung-Hwan Yeo
IPC分类号： H01L27/108
CPC分类号： H01L29/7883 , H01L27/108 , H01L27/10802 , H01L29/42336 , H01L29/42392 , H01L29/66825 , H01L29/7841
摘要： A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

10. 发明申请

US20060131666A1 Field effect transistor with buried gate pattern 有权
标题翻译：具有掩埋栅极图案的场效应晶体管
公开(公告)号：US20060131666A1
公开(公告)日：2006-06-22
申请号：US11241611
申请日：2005-09-30
申请人： Ming Li , Dong-Uk Choi , Chang-Woo Oh , Dong-Won Kim , Min-Sang Kim , Sung-Hwan Kim , Kyoung-Hwan Yeo
发明人： Ming Li , Dong-Uk Choi , Chang-Woo Oh , Dong-Won Kim , Min-Sang Kim , Sung-Hwan Kim , Kyoung-Hwan Yeo
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L27/108 , H01L27/10802 , H01L29/42336 , H01L29/42392 , H01L29/66825 , H01L29/7841
摘要： A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.
摘要翻译：场效应晶体管包括通过被隧道绝缘膜包围而电隔离的掩埋栅极图案。场效应晶体管还包括由源极和漏极区域浮置的沟道区，栅极绝缘膜和隧道绝缘膜。掩埋栅极图案和隧道绝缘膜延伸到源极和漏极区域。因此，场效应晶体管有效地将电荷载流子存储在掩埋栅极图案和浮动沟道区域中。

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