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1. 发明申请

US20080184006A1 Method and System for Preloading Page Using Control Flow 有权
标题翻译：使用控制流预加载页面的方法和系统
公开(公告)号：US20080184006A1
公开(公告)日：2008-07-31
申请号：US11833003
申请日：2007-08-02
申请人： Min-Soo Moon , Chan Ik Park
发明人： Min-Soo Moon , Chan Ik Park
IPC分类号： G06F12/02
CPC分类号： G06F8/4442
摘要： A method and system for page preloading using a control flow are provided. The method includes extracting preload page information from one or more pages in a first program code, and generating a second program code including the first program code and the extracted preload page information. The second program code is stored in non-volatile memory. When loading a page from the second program code stored in the non-volatile memory into main memory, preloading one or more pages from the non-volatile memory based on the preload page information stored in the loaded page.
摘要翻译：提供了一种使用控制流程进行页面预加载的方法和系统。该方法包括从第一程序代码中的一个或多个页面提取预加载页面信息，以及生成包括第一程序代码和所提取的预加载页面信息的第二程序代码。第二个程序代码存储在非易失性存储器中。当将存储在非易失性存储器中的第二程序代码的页面加载到主存储器中时，基于存储在加载的页面中的预加载页面信息，从非易失性存储器预加载一个或多个页面。

2. 发明授权

US08732413B2 Method and system for preloading page using control flow 有权
标题翻译：使用控制流预加载页面的方法和系统
公开(公告)号：US08732413B2
公开(公告)日：2014-05-20
申请号：US11833003
申请日：2007-08-02
申请人： Min-Soo Moon , Chan Ik Park
发明人： Min-Soo Moon , Chan Ik Park
IPC分类号： G06F12/00
CPC分类号： G06F8/4442
摘要： A method and system for page preloading using a control flow are provided. The method includes extracting preload page information from one or more pages in a first program code, and generating a second program code including the first program code and the extracted preload page information. The second program code is stored in non-volatile memory. When loading a page from the second program code stored in the non-volatile memory into main memory, preloading one or more pages from the non-volatile memory based on the preload page information stored in the loaded page.
摘要翻译：提供了一种使用控制流程进行页面预加载的方法和系统。该方法包括从第一程序代码中的一个或多个页面提取预加载页面信息，以及生成包括第一程序代码和所提取的预加载页面信息的第二程序代码。第二个程序代码存储在非易失性存储器中。当将存储在非易失性存储器中的第二程序代码的页面加载到主存储器中时，基于存储在加载的页面中的预加载页面信息，从非易失性存储器预加载一个或多个页面。

3. 发明授权

US08478928B2 Data storage device and information processing system incorporating data storage device 有权
标题翻译：数据存储设备和信息处理系统结合数据存储设备
公开(公告)号：US08478928B2
公开(公告)日：2013-07-02
申请号：US12764464
申请日：2010-04-21
申请人： Tae Hack Lee , Sang Kyoo Jeong , Myung Hyun Jo , Chan Ik Park
发明人： Tae Hack Lee , Sang Kyoo Jeong , Myung Hyun Jo , Chan Ik Park
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F1/266 , Y02D10/13
摘要： A data storage device comprises a plurality of memory devices and a memory controller. The memory controller exchanges data with the memory devices via a plurality of channels. The memory controller decodes an external command to generate a driving power mode and accesses the memory devices according to the driving power mode.
摘要翻译：数据存储装置包括多个存储装置和存储器控制器。存储器控制器通过多个通道与存储器件交换数据。存储器控制器解码外部命令以产生驱动功率模式，并根据驱动功率模式访问存储器件。

4. 发明授权

US07788441B2 Method for initializing and operating flash memory file system and computer-readable medium storing related program 有权
标题翻译：闪存文件系统的初始化和运行方法以及存储相关程序的计算机可读介质
公开(公告)号：US07788441B2
公开(公告)日：2010-08-31
申请号：US11730652
申请日：2007-04-03
申请人： Yang Sup Lee , Chan Ik Park , Jae Sung Jung
发明人： Yang Sup Lee , Chan Ik Park , Jae Sung Jung
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7211
摘要： A method for initializing and operating a flash memory file system and a computer-readable medium storing a program adapted to perform the method are disclosed. The method includes programming the flash memory file system in order to conceptually divide logical blocks into logical groups, and storing erasure data for one of the logical groups in a first region of a meta block. The method also includes loading erasure data for one logical group into an external memory device and mapping the logical blocks of the current logical group to the physical blocks in accordance with the erasure data loaded into the external memory device. The method also includes storing data of a data file in a data block of a flash memory device in accordance with the mapping of the logical blocks to the physical blocks.
摘要翻译：公开了一种用于初始化和操作闪速存储器文件系统的方法以及存储适于执行该方法的程序的计算机可读介质。该方法包括对闪速存储器文件系统进行编程，以在概念上将逻辑块划分为逻辑组，并将一个逻辑组的擦除数据存储在元块的第一区域中。该方法还包括将一个逻辑组的擦除数据加载到外部存储器件中，并根据加载到外部存储器件中的擦除数据将当前逻辑组的逻辑块映射到物理块。该方法还包括根据逻辑块到物理块的映射将数据文件的数据存储在闪存设备的数据块中。

5. 发明申请

US20120216094A1 Controller, A Method Of Operating The Controller And A Memory System 有权
标题翻译：控制器，操作控制器和存储器系统的方法
公开(公告)号：US20120216094A1
公开(公告)日：2012-08-23
申请号：US13070620
申请日：2011-03-24
申请人： Sung Joo Yoo , Nam-Wook Kang , Chan Ik Park , Hyun Jin Choi
发明人： Sung Joo Yoo , Nam-Wook Kang , Chan Ik Park , Hyun Jin Choi
IPC分类号： H03M13/09 , G06F11/08
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： The present disclosure provides a controller which comprises a command generator configured to generate a command to non volatile memory, and buffer configured to receive a first data and a second data and configured to combine the first data and the second data, an ECC unit configured to perform the ECC decoding. And the first page data may include at least one error bit corresponding to an error location table and the second page data may include at least one original bit which can be replaced with the error bit. The buffer may replace the at least one error bit with the said at least one original bit. The error location table may save information of location for the repeated error bit.
摘要翻译：本公开提供一种控制器，其包括命令发生器，其被配置为生成对非易失性存储器的命令，以及配置为接收第一数据和第二数据并被配置为组合第一数据和第二数据的缓冲器，ECC单元，被配置为执行ECC解码。并且第一页数据可以包括对应于错误位置表的至少一个错误位，并且第二页数据可以包括可以用错误位替换的至少一个原始位。所述缓冲器可以用所述至少一个原始位替换所述至少一个错误位。错误位置表可以保存重复错误位的位置信息。

6. 发明授权

US08769378B2 Controller, a method of operating the controller and a memory system 有权
标题翻译：控制器，操作控制器和存储器系统的方法
公开(公告)号：US08769378B2
公开(公告)日：2014-07-01
申请号：US13070620
申请日：2011-03-24
申请人： Sung Joo Yoo , Nam-Wook Kang , Chan Ik Park , Hyun Jin Choi
发明人： Sung Joo Yoo , Nam-Wook Kang , Chan Ik Park , Hyun Jin Choi
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： The present disclosure provides a controller which comprises a command generator configured to generate a command to non volatile memory, and buffer configured to receive a first data and a second data and configured to combine the first data and the second data, an ECC unit configured to perform the ECC decoding. And the first page data may include at least one error bit corresponding to an error location table and the second page data may include at least one original bit which can be replaced with the error bit. The buffer may replace the at least one error bit with the said at least one original bit. The error location table may save information of location for the repeated error bit.
摘要翻译：本公开提供一种控制器，其包括命令发生器，其被配置为生成对非易失性存储器的命令，以及配置为接收第一数据和第二数据并被配置为组合第一数据和第二数据的缓冲器，ECC单元，被配置为执行ECC解码。并且第一页数据可以包括对应于错误位置表的至少一个错误位，并且第二页数据可以包括可以用错误位替换的至少一个原始位。所述缓冲器可以用所述至少一个原始位替换所述至少一个错误位。错误位置表可以保存重复错误位的位置信息。

7. 发明授权

US08615702B2 Method and apparatus for correcting errors in memory device 有权
标题翻译：用于校正存储器件中的错误的方法和装置
公开(公告)号：US08615702B2
公开(公告)日：2013-12-24
申请号：US13236701
申请日：2011-09-20
申请人： Sung Joo Yoo , Nam-Wook Kang , Chan Ik Park , Hyun Jin Choi
发明人： Sung Joo Yoo , Nam-Wook Kang , Chan Ik Park , Hyun Jin Choi
IPC分类号： H03M13/00
CPC分类号： G06F11/1012
摘要： A memory controller analyzes read data received from a memory device and first error correction code (ECC) data of the read data. A control unit generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than a number of error bits that can be corrected using the first ECC data. An ECC block generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in each of the sub-data. The control unit transmits each of the sub-data, the first ECC data and the second ECC data to the memory device.
摘要翻译：存储器控制器分析从存储器件接收的读取数据和读取数据的第一纠错码（ECC）数据。控制单元从要写入存储器件的写入数据产生多个子数据，其中读取数据中的错误位数大于可以使用第一ECC数据校正的错误位数。 ECC块通过使用基本上相同的算法来校正每个子数据中的错误来生成第一ECC数据和第二ECC数据。控制单元将每个子数据，第一ECC数据和第二ECC数据发送到存储器件。

8. 发明申请

US20120151294A1 METHOD AND APPARATUS FOR CORRECTING ERRORS IN MEMORY DEVICE 有权
标题翻译：用于校正存储器件中的错误的方法和装置
公开(公告)号：US20120151294A1
公开(公告)日：2012-06-14
申请号：US13236701
申请日：2011-09-20
申请人： Sung Joo Yoo , Nam-Wook Kang , Chan Ik Park , Hyun Jin Choi
发明人： Sung Joo Yoo , Nam-Wook Kang , Chan Ik Park , Hyun Jin Choi
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1012
摘要： A memory controller analyzes read data received from a memory device and first error correction code (ECC) data of the read data. A control unit generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than a number of error bits that can be corrected using the first ECC data. An ECC block generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in each of the sub-data. The control unit transmits each of the sub-data, the first ECC data and the second ECC data to the memory device.
摘要翻译：存储器控制器分析从存储器件接收的读取数据和读取数据的第一纠错码（ECC）数据。控制单元从要写入存储器件的写入数据产生多个子数据，其中读取数据中的错误位数大于可以使用第一ECC数据校正的错误位数。 ECC块通过使用基本上相同的算法来校正每个子数据中的错误来生成第一ECC数据和第二ECC数据。控制单元将每个子数据，第一ECC数据和第二ECC数据发送到存储器件。

9. 发明授权

US5778520A Method of making an assembly package in an air tight cavity and a product made by the method 失效
标题翻译：在气密腔中制造组装包的方法和由该方法制成的产品
公开(公告)号：US5778520A
公开(公告)日：1998-07-14
申请号：US675110
申请日：1996-07-03
申请人： Jong Tae Kim , Chan Ik Park
发明人： Jong Tae Kim , Chan Ik Park
IPC分类号： H01L23/057 , H01L23/10 , H01L23/31
CPC分类号： H01L23/057 , H01L23/10 , H01L24/97 , H01L2224/48091 , H01L2224/48247 , H01L2924/1423 , H01L2924/181 , Y10T29/49121
摘要： A method of making an assembly having an air tight cavity for holding an element therein and having a plurality of thin and flat planar conductive leads extending outwardly from the cavity for providing electrically conductive paths from the element held within the cavity, and a conductive plate for supporting the circuitry, comprising (a) injecting a liquified thermosetting epoxy into a die and solidifying the epoxy by heat curing to form a dielectric frame that is configured such that the inner end and tip portions of the conductive leads are buried in the frame, the flat surfaces of the intermediate portions of the conductive leads are exposed in a common plane and the outer end portions of the conductive leads extend outside the epoxy, (b) bonding the bottom surface of the resulting dielectric frame to the outer periphery of the conductive base plate, (c) plating the exposed flat surfaces of the conductive leads and the conductive base plate with a conductive material, (d) connecting the circuitry disposed within the opening to the conductive base plate and the exposed flat surfaces of the conductive leads and (f) enclosing the resulting connected circuitry to form an air tight cavity.
摘要翻译：一种制造组件的方法，所述组件具有用于将元件保持在其中的气密腔，并且具有多个从所述空腔向外延伸的薄且平坦的平面导电引线，用于提供从所述空腔内的元件提供导电路径;以及导电板，支持电路，包括（a）将液化的热固性环氧树脂注入模具中并通过热固化固化环氧树脂以形成电介体框架，其被配置为使得导电引线的内端部和顶端部分被埋在框架中，导电引线的中间部分的平坦表面暴露在公共平面中，并且导电引线的外端部延伸到环氧树脂外部，（b）将所得电介质框架的底表面接合到导电基底的外周边（c）用导电材料电镀导电引线和导电基板的暴露的平坦表面，（d）连接设置在导电基板的开口内的电路和导电引线的暴露的平坦表面，以及（f）封装所产生的连接电路以形成气密腔。

10. 发明授权

US09817652B2 Data storage device and method for reducing firmware update time and data processing system including the device 有权
公开(公告)号：US09817652B2
公开(公告)日：2017-11-14
申请号：US14865415
申请日：2015-09-25
申请人： Sang Hoon Choi , Sung Chul Kim , Hyun Koo Kim , Chan Ik Park , Han Deok Lee
发明人： Sang Hoon Choi , Sung Chul Kim , Hyun Koo Kim , Chan Ik Park , Han Deok Lee
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F8/65 , G06F8/63 , G06F8/654
摘要： A data storage device for reducing a firmware update time includes a non-volatile memory configured to store a firmware update image which will replace a current firmware image, a first volatile memory, and a processor configured to control an operation of the non-volatile memory and an operation of the first volatile memory. When a first code included in the current firmware image is executed by the processor, the first code generates data necessary for an operation of the data storage device and stores the data in the first volatile memory. When a second code included in the firmware update image is executed by the first code, the second code accesses and uses the data that has been stored in the first volatile memory.

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