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1. 发明申请

US20070172985A1 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US20070172985A1
公开(公告)日：2007-07-26
申请号：US11645042
申请日：2006-12-26
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chain-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chain-Chi Lin
IPC分类号： H01L21/00
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/48145 , H01L2225/06506 , H01L2225/06524 , H01L2225/06541 , H01L2924/01019 , H01L2924/01078 , H01L2924/00012
摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a metal; (g) removing the dry film, and patterning the conductive layer; (h) removing a part of the metal in the blind hole to form a space; (i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) forming a solder on the lower end of the conductive layer, wherein the melting point of the solder is lower than that of the metal; (k) stacking a plurality of the wafers, and performing a reflow process; and (l) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.
摘要翻译：本发明涉及三维包装及其制造方法。该方法包括：（a）提供晶片; （b）在所述晶片中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）在导电层上形成干膜; （f）用金属填充盲孔; （g）去除干膜，图案化导电层; （h）去除盲孔中的金属的一部分以形成空间; （i）去除所述晶片的所述第二表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （j）在导电层的下端形成焊料，其中焊料的熔点低于金属的熔点; （k）堆叠多个晶片，并进行回流处理; 和（l）切割堆叠的晶片，以便形成多个三维封装。因此，导电层的下端和其上的焊料被“插入”到下晶片的空间中，以增强导电层和焊料之间的接合，并且有效地降低了三层结构的整体高度，加入后立体包装。

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