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1. 发明申请

US20080237586A1 Semiconductor Integrated Test Structures For Electron Beam Inspection of Semiconductor Wafers 有权
标题翻译：用于半导体晶片的电子束检测的半导体集成测试结构
公开(公告)号：US20080237586A1
公开(公告)日：2008-10-02
申请号：US11694449
申请日：2007-03-30
申请人： Min Chul Sun , Scott Jansen , Randy Mann , Oliver D. Patterson
发明人： Min Chul Sun , Scott Jansen , Randy Mann , Oliver D. Patterson
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/32
摘要： Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.
摘要翻译：半导体集成测试结构被设计用于半导体晶片的电子束检查。测试结构包括与晶片上形成的集成电路的图形特征同时形成在晶片的指定测试区域中的图案特征。测试结构包括导电结构，其被设计成能够在缺陷和非缺陷特征（或给定特征的有缺陷和非缺陷部分）之间进行差分充电，以便于CMOS器件的电压对比度缺陷检测，例如使用单个，尽管晶片衬底或其他元件/特征中存在p / n结，但是低能电子束扫描也是如此。

2. 发明授权

US07679083B2 Semiconductor integrated test structures for electron beam inspection of semiconductor wafers 有权
标题翻译：半导体晶圆电子束检测半导体集成测试结构
公开(公告)号：US07679083B2
公开(公告)日：2010-03-16
申请号：US11694449
申请日：2007-03-30
申请人： Min Chul Sun , Scott Jansen , Randy Mann , Oliver D. Patterson
发明人： Min Chul Sun , Scott Jansen , Randy Mann , Oliver D. Patterson
IPC分类号： H01L23/58
CPC分类号： H01L22/32
摘要： Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.
摘要翻译：半导体集成测试结构被设计用于半导体晶片的电子束检查。测试结构包括与晶片上形成的集成电路的图形特征同时形成在晶片的指定测试区域中的图案特征。测试结构包括导电结构，其被设计成能够在缺陷和非缺陷特征（或给定特征的有缺陷和非缺陷部分）之间进行差分充电，以便于CMOS器件的电压对比度缺陷检测，例如使用单个，尽管晶片衬底或其他元件/特征中存在p / n结，但是低能电子束扫描也是如此。

3. 发明授权

US07772866B2 Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection 失效
标题翻译：集成电路检测信号强度与表面电压映射的结构和方法
公开(公告)号：US07772866B2
公开(公告)日：2010-08-10
申请号：US11683058
申请日：2007-03-07
申请人： Oliver D. Patterson , Horatio Seymour Wildman , Min-Chul Sun
发明人： Oliver D. Patterson , Horatio Seymour Wildman , Min-Chul Sun
IPC分类号： G01R31/02
CPC分类号： H01L22/34
摘要： Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.
摘要翻译：本发明的实施例提供了用于集成电路检查的测试结构。测试结构可以与一个或多个集成电路一起制造在半导体晶圆上。测试结构可以包括用于参考电压的公共参考点; 多个降压装置连接到公共参考点; 并且多个电子收集垫分别连接到多个降压装置的多个接触点。在集成电路的检查期间由多个电子收集板所示的亮度可以与预定电压相关联。

4. 发明申请

US20080217612A1 STRUCTURE AND METHOD OF MAPPING SIGNAL INTENSITY TO SURFACE VOLTAGE FOR INTEGRATED CIRCUIT INSPECTION 失效
标题翻译：将信号强度映射到集成电路检测的表面电压的结构和方法
公开(公告)号：US20080217612A1
公开(公告)日：2008-09-11
申请号：US11683058
申请日：2007-03-07
申请人： Oliver D. Patterson , Horatio Seymour Wildman , Min-Chul Sun
发明人： Oliver D. Patterson , Horatio Seymour Wildman , Min-Chul Sun
IPC分类号： H01L23/58
CPC分类号： H01L22/34
摘要： Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.
摘要翻译：本发明的实施例提供了用于集成电路检查的测试结构。测试结构可以与一个或多个集成电路一起制造在半导体晶片上。测试结构可以包括用于参考电压的公共参考点; 多个降压装置连接到公共参考点; 并且多个电子收集垫分别连接到多个降压装置的多个接触点。在集成电路的检查期间由多个电子收集板所示的亮度可以与预定电压相关联。

5. 发明授权

US09291665B2 Evaluating transistors with e-beam inspection 有权
标题翻译：用电子束检查评估晶体管
公开(公告)号：US09291665B2
公开(公告)日：2016-03-22
申请号：US13470645
申请日：2012-05-14
申请人： Oliver D. Patterson , Zhigang Song
发明人： Oliver D. Patterson , Zhigang Song
IPC分类号： G01R31/02 , G01R31/265 , G01R31/317 , G01R31/27
CPC分类号： G01R31/2653 , G01R31/275 , G01R31/31721
摘要： A test structure of a semiconductor wafer includes a series of electrical units connected electrically in series output-to-input in an open loop configuration. The series of electrical units is configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit. Each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates.
摘要翻译：半导体晶片的测试结构包括一系列在开环配置中以串联输出输入的电连接的电气单元。一系列电气单元被配置为具有交替的输出电压，使得每个电气单元被配置为输出与前一个电气单元的输出电压相反的电压。每个电单元被配置为当施加到该系列电气单元中的第一电气单元的输入电压交替时，具有交替的输出电压。

6. 发明授权

US08841933B2 Inspection tool and methodology for three dimensional voltage contrast inspection 有权
标题翻译：三维电压对比检查的检查工具和方法
公开(公告)号：US08841933B2
公开(公告)日：2014-09-23
申请号：US12878089
申请日：2010-09-09
申请人： Oliver D. Patterson
发明人： Oliver D. Patterson
IPC分类号： G01R31/02 , G01R31/307
CPC分类号： G01R31/307 , G06T7/0004
摘要： A system and method for improved voltage contrast inspection is disclosed. In one embodiment the temporal response to voltage contrast is considered to find an optimal acquisition time. In another embodiment, multiple optimal acquisition times are identified. The identified acquisition times are used in voltage contrast inspection of semiconductor fabrication, and are well-suited to SOI technology.
摘要翻译：公开了一种用于改进电压对比度检测的系统和方法。在一个实施例中，对电压对比度的时间响应被认为是找到最佳采集时间。在另一个实施例中，识别出多个最佳采集时间。所识别的采集时间用于半导体制造的电压对比度检查，并且非常适合于SOI技术。

7. 发明授权

US08750597B2 Robust inspection alignment of semiconductor inspection tools using design information 失效
标题翻译：使用设计信息对半导体检测工具进行可靠的检查对齐
公开(公告)号：US08750597B2
公开(公告)日：2014-06-10
申请号：US13303440
申请日：2011-11-23
申请人： Oliver D. Patterson , Kevin T. Wu
发明人： Oliver D. Patterson , Kevin T. Wu
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： A method of performing inspection alignment point selection for semiconductor devices includes importing, with a computer device, one or more semiconductor design files corresponding to an area of a semiconductor die; aligning a design taken from the one or more semiconductor design files with an image taken from a die of a semiconductor wafer; and selecting an alignment point and recording a portion of the design file corresponding to the alignment point as a master reference image.
摘要翻译：对于半导体器件执行检查对准点选择的方法包括使用计算机设备导入对应于半导体管芯的区域的一个或多个半导体设计文件; 将从一个或多个半导体设计文件获取的设计与从半导体晶片的管芯获取的图像对准; 并且选择对准点并记录与对准点对应的设计文件的一部分作为主参照图像。

8. 发明申请

US20110037493A1 PROBE-ABLE VOLTAGE CONTRAST TEST STRUCTURES 失效
标题翻译：探头电压对比测试结构
公开(公告)号：US20110037493A1
公开(公告)日：2011-02-17
申请号：US12539732
申请日：2009-08-12
申请人： William J. Cote , Yi Feng , Oliver D. Patterson
发明人： William J. Cote , Yi Feng , Oliver D. Patterson
IPC分类号： G01R1/06 , G01R31/00
CPC分类号： G01R31/2884
摘要： Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.
摘要翻译：使用其检测缺陷的测试结构和方法。包括第一，第二和第三探针焊盘的可探测电压对比度（VC）梳状测试结构，包括接地尖齿的梳状结构，接地尖端之间的浮动尖齿，与每个浮动齿的端部耦合的开关装置，以及将所述浮动尖齿连接到所述第二探针焊盘，并且所述第三探针焊盘是控制所述切换装置的控制焊盘。一种可探测的VC蛇形测试结构，包括第一，第二，第三和第四探针焊盘，包括接地尖齿的梳状结构，接地尖齿之间的浮动尖齿和连接在第二和第三探针焊盘之间的每个浮动齿，切换连接到每个浮动齿的端部并且将浮动尖齿连接到第二和第三探针焊盘的装置，第四探针焊盘是控制开关装置的控制焊盘。

9. 发明授权

US07518190B2 Grounding front-end-of-line structures on a SOI substrate 有权
标题翻译：在SOI衬底上接地前端结构
公开(公告)号：US07518190B2
公开(公告)日：2009-04-14
申请号：US11308408
申请日：2006-03-22
申请人： William J. Cote , Oliver D. Patterson
发明人： William J. Cote , Oliver D. Patterson
IPC分类号： H01L23/62
CPC分类号： H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.
摘要翻译：公开了用于在绝缘体上硅（SOI）衬底上接地栅叠层和/或硅有源区前线结构的结构和方法，其可用作VC检验的测试结构。在一个实施例中，结构包括其上具有SOI衬底的接地体硅衬底，SOI衬底包括绝缘体上硅（SOI）层和掩埋氧化物（BOX）层; 所述硅有源区在所述SOI层内具有至少一个指状元件，所述至少一个指状元件由浅沟槽隔离（STI）层隔离; 以及与所述至少一个指状元件相交并且穿过所述STI层和所述BOX层延伸到所述接地体硅衬底的多晶硅地，所述多晶硅接地与所述硅有源区和所述接地体硅衬底接触。

10. 发明申请

US20080225284A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR OPTIMIZING INSPECTION RECIPES USING PROGRAMMED DEFECTS 审中-公开
标题翻译：使用编程缺陷优化检查录像的方法，设备和计算机程序产品
公开(公告)号：US20080225284A1
公开(公告)日：2008-09-18
申请号：US12127951
申请日：2008-05-28
申请人： Oliver D. Patterson , Maryjane Brodsky , Kourosh Nafisi
发明人： Oliver D. Patterson , Maryjane Brodsky , Kourosh Nafisi
IPC分类号： G01N21/00
CPC分类号： G01N21/93 , G01N21/956
摘要： A method and computer program product for implementing inspection recipe services are provided. The method includes defining a modified reticle pitch for use in inspecting programmed defects on a test structure, the modified reticle pitch extending the distance of one reticle field plus a portion of an adjacent reticle field on the test structure. The test structure includes a number of arrays linearly arranged on the test structure and spaced equidistant, and each of the arrays corresponds to a reticle field and includes a number of cells. The method also includes using the modified reticle field pitch and an alignment site on the test structure to perform a random mode inspection of the test structure.
摘要翻译：提供了一种用于实施检验食谱服务的方法和计算机程序产品。该方法包括定义用于检查测试结构上的编程缺陷的修改的掩模版间距，修改的标线间距将一个掩模版场的距离加上测试结构上相邻掩模版场的一部分。测试结构包括线性地布置在测试结构上并且间隔等间隔的多个阵列，并且每个阵列对应于掩模版场并且包括多个单元。该方法还包括使用修改的标线场场间距和测试结构上的对准位置来执行测试结构的随机模式检查。

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